[PATCH] arm64: gic: Add power up sequence for GIC-600

[Tom Rini]

On Wed, Mar 06, 2024 at 04:54:41PM +0530, Venkatesh Yadav Abbarapu wrote:

> Arm's GIC-600 features a Power Register (GICR_PWRR),
> which needs to be programmed to enable redistributor
> operation. Power on the redistributor and  wait until
> the power on state is reflected by checking the bit
> GICR_PWRR.RDPD == 0. While running U-Boot in EL3
> without enabling this register, GICR_WAKER.ChildrenAsleep
> bit is not getting cleared and loops infinitely.
> This register(GICR_PWRR) must be programmed to mark the frame
> as powered on, before accessing other registers in the frame.
> Rest of initialization sequence remains the same.
> 
> ARM GIC-600 IP complies with ARM GICv3 architecture.
> Enable this config if GIC-600 IP present.
> 
> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu at amd.com>

Applied to u-boot/next, thanks!

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20240320/0a99d198/attachment.sig>