[PATCH v2 6/6] cmd: nand: Add new optional sub-command 'onfi'

[Mihai.Sain at microchip.com]

Hi Alex,

------------------------------------------

Override the ONFI timing mode at runtime.

Signed-off-by: Alexander Dahl <ada at thorsis.com>
---

Tested-by: Mihai Sain <mihai.sain at microchip.com>

I tested your new command on a new board/soc sam9x75-curiosity 😊
I find it very very useful !
I also rounded the master clock to 270 MHz 😊
Thanks.

=> nand info

Device 0: nand0, sector size 256 KiB
  Manufacturer  MACRONIX
  Model         MX30LF4G28AD
  Device size        512 MiB
  Page size         4096 b
  OOB size           256 b
  Erase size      262144 b
  ecc strength         8 bits
  ecc step size      512 b
  subpagesize       4096 b
  options       0x40004200
  bbt options   0x00028000

=> hsmc decode

MCK rate: 270 MHz

SMC_SETUP2:     0x00000004
SMC_PULSE2:     0x0c070d05
SMC_CYCLE2:     0x000c000d
SMC_MODE2:      0x001f0003
NCS_RD: setup: 0 (0 ns), pulse: 12 (36 ns), hold: 0 (0 ns), cycle: 12 (36 ns)
   NRD: setup: 0 (0 ns), pulse: 7 (21 ns), hold: 5 (15 ns), cycle: 12 (36 ns)
NCS_WR: setup: 0 (0 ns), pulse: 13 (39 ns), hold: 0 (0 ns), cycle: 13 (39 ns)
   NWE: setup: 4 (12 ns), pulse: 5 (15 ns), hold: 4 (12 ns), cycle: 13 (39 ns)
Standard read applied
TDF optimization enabled
TDF cycles: 15 (45 ns)
Data Bus Width: 8-bit bus
NWAIT Mode: 0
Write operation controlled by NWE signal
Read operation controlled by NRD signal

=> nand onfi 2
=> hsmc decode

MCK rate: 270 MHz

SMC_SETUP2:     0x00000003
SMC_PULSE2:     0x0e090e06
SMC_CYCLE2:     0x000e000e
SMC_MODE2:      0x001f0003
NCS_RD: setup: 0 (0 ns), pulse: 14 (42 ns), hold: 0 (0 ns), cycle: 14 (42 ns)
   NRD: setup: 0 (0 ns), pulse: 9 (27 ns), hold: 5 (15 ns), cycle: 14 (42 ns)
NCS_WR: setup: 0 (0 ns), pulse: 14 (42 ns), hold: 0 (0 ns), cycle: 14 (42 ns)
   NWE: setup: 3 (9 ns), pulse: 6 (18 ns), hold: 5 (15 ns), cycle: 14 (42 ns)
Standard read applied
TDF optimization enabled
TDF cycles: 15 (45 ns)
Data Bus Width: 8-bit bus
NWAIT Mode: 0
Write operation controlled by NWE signal
Read operation controlled by NRD signal

=> nand onfi 1
=> hsmc decode

MCK rate: 270 MHz

SMC_SETUP2:     0x00000003
SMC_PULSE2:     0x110a1109
SMC_CYCLE2:     0x00110011
SMC_MODE2:      0x001f0003
NCS_RD: setup: 0 (0 ns), pulse: 17 (51 ns), hold: 0 (0 ns), cycle: 17 (51 ns)
   NRD: setup: 0 (0 ns), pulse: 10 (30 ns), hold: 7 (21 ns), cycle: 17 (51 ns)
NCS_WR: setup: 0 (0 ns), pulse: 17 (51 ns), hold: 0 (0 ns), cycle: 17 (51 ns)
   NWE: setup: 3 (9 ns), pulse: 9 (27 ns), hold: 5 (15 ns), cycle: 17 (51 ns)
Standard read applied
TDF optimization enabled
TDF cycles: 15 (45 ns)
Data Bus Width: 8-bit bus
NWAIT Mode: 0
Write operation controlled by NWE signal
Read operation controlled by NRD signal

=> nand onfi 3
=> hsmc decode

MCK rate: 270 MHz

SMC_SETUP2:     0x00000004
SMC_PULSE2:     0x0c070d05
SMC_CYCLE2:     0x000c000d
SMC_MODE2:      0x001f0003
NCS_RD: setup: 0 (0 ns), pulse: 12 (36 ns), hold: 0 (0 ns), cycle: 12 (36 ns)
   NRD: setup: 0 (0 ns), pulse: 7 (21 ns), hold: 5 (15 ns), cycle: 12 (36 ns)
NCS_WR: setup: 0 (0 ns), pulse: 13 (39 ns), hold: 0 (0 ns), cycle: 13 (39 ns)
   NWE: setup: 4 (12 ns), pulse: 5 (15 ns), hold: 4 (12 ns), cycle: 13 (39 ns)
Standard read applied
TDF optimization enabled
TDF cycles: 15 (45 ns)
Data Bus Width: 8-bit bus
NWAIT Mode: 0
Write operation controlled by NWE signal
Read operation controlled by NRD signal

=> nand torture 0x800000 0x800000

NAND torture: device 0 offset 0x800000 size 0x800000 (block size 0x40000)
 Passed: 32, failed: 0

=> clk dump

24000000              1        |       |-- mainck
 1080000000           1        |       |   |-- plla_fracck
 1080000000           1        |       |   |   |-- plla_divpmcck
 1080000000           1        |       |   |   |   `-- mck_pres
 270000000            8        |       |   |   |       `-- mck_div

Best regards,
Mihai Sain