[PATCH v3 1/2] arm: socfpga: arria10: add option to reprogram the FPGA every reboot

[Chee, Tien Fong]

> -----Original Message-----
> From: Michał Barnaś <barnas at google.com>
> Sent: Wednesday, March 20, 2024 2:18 AM
> To: u-boot at lists.denx.de
> Cc: Michał Barnaś <barnas at google.com>; Dinh Nguyen
> <dinguyen at kernel.org>; Marek Vasut <marex at denx.de>; Simon Glass
> <sjg at chromium.org>; Simon Goldschmidt
> <simon.k.r.goldschmidt at gmail.com>; Chee, Tien Fong
> <tien.fong.chee at intel.com>; Tom Rini <trini at konsulko.com>
> Subject: [PATCH v3 1/2] arm: socfpga: arria10: add option to reprogram the
> FPGA every reboot
> 
> Add Kconfig that enables FPGA reprogramming with warm boot on Arria 10.
> This option allows to change the bitstream on the filesystem and apply
> changes with warm reboot without the need for a power cycle.
> 
> Signed-off-by: Michał Barnaś <barnas at google.com>
> ---
> 
> Changes in v3:
> - Rebase on current master branch
> - Drop the TARGET_ prefix in Kconfig
> - Remove #ifdefs and use IS_ENABLED
> 
> Changes in v2:
> - Rebase on current master branch
> 
>  arch/arm/mach-socfpga/Kconfig   | 8 ++++++++
>  arch/arm/mach-socfpga/spl_a10.c | 8 ++++++--
>  2 files changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-
> socfpga/Kconfig index 114d243812..a89bd8ca58 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -80,6 +80,14 @@ config TARGET_SOCFPGA_ARRIA10
>  	imply FPGA_SOCFPGA
>  	imply SPL_USE_TINY_PRINTF
> 
> +config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
> +	bool "Always reprogram Arria 10 FPGA"
> +	depends on TARGET_SOCFPGA_ARRIA10
> +	help
> +	  Arria 10 FPGA is only programmed during the cold boot.
> +	  This option forces the FPGA to be reprogrammed every reboot,
> +	  allowing to change the bitstream and apply it with warm reboot.
> +
>  config TARGET_SOCFPGA_CYCLONE5
>  	bool
>  	select TARGET_SOCFPGA_GEN5
> diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-
> socfpga/spl_a10.c index 9edbbf4a29..3981d2d4f1 100644
> --- a/arch/arm/mach-socfpga/spl_a10.c
> +++ b/arch/arm/mach-socfpga/spl_a10.c
> @@ -122,7 +122,10 @@ void spl_board_init(void)
>  	arch_early_init_r();
> 
>  	/* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
> -	if (is_fpgamgr_user_mode()) {
> +	if
> ((IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) &&
> +	     is_regular_boot_valid()) ||
> +
> (!IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) &&
> +	     is_fpgamgr_user_mode())) {
>  		ret = config_pins(gd->fdt_blob, "shared");
>  		if (ret)
>  			return;
> @@ -130,7 +133,8 @@ void spl_board_init(void)
>  		ret = config_pins(gd->fdt_blob, "fpga");
>  		if (ret)
>  			return;
> -	} else if (!is_fpgamgr_early_user_mode()) {
> +	} else if
> (IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) ||
> +		   !is_fpgamgr_early_user_mode()) {
>  		/* Program IOSSM(early IO release) or full FPGA */
>  		fpgamgr_program(buf, FPGA_BUFSIZ, 0);
> 
> --
> 2.44.0.291.gc1ea87d7ee-goog

Reviewed-by: Tien Fong Chee <tien.fong.chee at intel.com>

Regards
Tien Fong