[GIT PULL] u-boot-riscv/master

[Leo Liang]

Hi Tom,

The following changes since commit ff0de1f0557ed7d2dab47ba976a37347a1fdc432:

  Merge patch series "Update PHYTEC SOM Detection" (2024-04-29 10:56:05 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 19b762cf83f68b9d9a1f14e75d75781cedf4049f:

  board: starfive: Rename spl_soc_init() to spl_dram_init() (2024-05-02 00:01:18 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20596 
----------------------------------------------------------------

- RISC-V: cmd: Add SBI implementation ID and extension ID
- Board: Rename spl_soc_init to spl_dram_init
- Board: milkv_duo: Add SPI NOR flash, Ethernet, Sysreset support

----------------------------------------------------------------
Heinrich Schuchardt (2):
      cmd: sbi: add Supervisor Software Events extension
      cmd: sbi: add coreboot and oreboot implementation IDs

Kongyang Liu (10):
      mmc: cv1800b: Add transmit tap delay config to fix write error
      sysreset: cv1800b: Add sysreset driver for cv1800b SoC
      board: sophgo: milkv_duo: Bind sysreset driver
      configs: milkv_duo: Add sysreset configs
      board: milkv_duo: Add init code for Milk-V Duo ethernet
      riscv: dts: sophgo: Add ethernet node
      configs: milkv_duo: Add ethernet configs
      spi: cv1800b: Add spi nor flash controller driver for cv1800b SoC
      riscv: dts: sophgo: Add spi nor flash controller node
      configs: milkv_duo: Add spi nor configs

Lukas Funke (2):
      board: sifive: Rename spl_soc_init() to spl_dram_init()
      board: starfive: Rename spl_soc_init() to spl_dram_init()

Yu Chien Peter Lin (1):
      riscv: andesv5: Set default cache line size to 64-bytes

 arch/riscv/cpu/andesv5/Kconfig           |   1 +
 arch/riscv/cpu/fu540/spl.c               |   2 +-
 arch/riscv/cpu/fu740/spl.c               |   2 +-
 arch/riscv/cpu/jh7110/spl.c              |   2 +-
 arch/riscv/dts/cv1800b-milkv-duo.dts     |  18 ++
 arch/riscv/dts/cv18xx.dtsi               |  40 ++++
 arch/riscv/include/asm/arch-fu540/spl.h  |   2 +-
 arch/riscv/include/asm/arch-fu740/spl.h  |   2 +-
 arch/riscv/include/asm/arch-jh7110/spl.h |   2 +-
 arch/riscv/include/asm/sbi.h             |   1 +
 board/sifive/unleashed/spl.c             |   4 +-
 board/sifive/unmatched/spl.c             |   4 +-
 board/sophgo/milkv_duo/Makefile          |   3 +-
 board/sophgo/milkv_duo/board.c           |  10 +
 board/sophgo/milkv_duo/ethernet.c        |  79 ++++++++
 board/sophgo/milkv_duo/ethernet.h        |  11 ++
 board/starfive/visionfive2/spl.c         |   4 +-
 cmd/riscv/sbi.c                          |   3 +
 configs/milkv_duo_defconfig              |  10 +
 drivers/mmc/cv1800b_sdhci.c              |   4 +-
 drivers/net/designware.c                 |   1 +
 drivers/spi/Kconfig                      |   8 +
 drivers/spi/Makefile                     |   1 +
 drivers/spi/cv1800b_spif.c               | 321 +++++++++++++++++++++++++++++++
 drivers/sysreset/Kconfig                 |   5 +
 drivers/sysreset/Makefile                |   1 +
 drivers/sysreset/sysreset_cv1800b.c      |  64 ++++++
 27 files changed, 591 insertions(+), 14 deletions(-)
 create mode 100644 board/sophgo/milkv_duo/ethernet.c
 create mode 100644 board/sophgo/milkv_duo/ethernet.h
 create mode 100644 drivers/spi/cv1800b_spif.c
 create mode 100644 drivers/sysreset/sysreset_cv1800b.c
 
 Best regards,
 Leo