[PATCH 1/2 v2] board: starfive: support Pine64 Star64 board

[H Bell]

Similar to the Milk-V Mars, The Star64 board contains few differences to the
VisionFive 2 boards, so can be part of the same U-boot build.

Signed-off-by: Henry Bell <dmoo_dv at protonmail.com>
Cc: ycliang at andestech.com
Cc: heinrich.schuchardt at canonical.com
---

Changes since v1

- Fix typos on naming
- Create pine64_star64 struct to be populated with PHY values once confirmed
---
 board/starfive/visionfive2/spl.c              | 85 +++++++++++++++++++
 .../visionfive2/starfive_visionfive2.c        |  4 +
 2 files changed, 89 insertions(+)

diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index ca61b5be22..248c6ba01d 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -86,6 +86,39 @@ static const struct starfive_vf2_pro starfive_verb[] = {
 		"tx-internal-delay-ps", "0"},
 };
 
+static const struct starfive_vf2_pro star64_pine64[] = {
+	{"/soc/ethernet at 16030000", "starfive,tx-use-rgmii-clk", NULL},
+	{"/soc/ethernet at 16040000", "starfive,tx-use-rgmii-clk", NULL},
+
+	{"/soc/ethernet at 16030000/mdio/ethernet-phy at 0",
+		"motorcomm,tx-clk-adj-enabled", NULL},
+	{"/soc/ethernet at 16030000/mdio/ethernet-phy at 0",
+		"motorcomm,tx-clk-100-inverted", NULL},
+	{"/soc/ethernet at 16030000/mdio/ethernet-phy at 0",
+		"motorcomm,tx-clk-1000-inverted", NULL},
+	{"/soc/ethernet at 16030000/mdio/ethernet-phy at 0",
+		"motorcomm,rx-clk-drv-microamp", "3970"},
+	{"/soc/ethernet at 16030000/mdio/ethernet-phy at 0",
+		"motorcomm,rx-data-drv-microamp", "2910"},
+	{"/soc/ethernet at 16030000/mdio/ethernet-phy at 0",
+		"rx-internal-delay-ps", "1900"},
+	{"/soc/ethernet at 16030000/mdio/ethernet-phy at 0",
+		"tx-internal-delay-ps", "1500"},
+
+	{"/soc/ethernet at 16040000/mdio/ethernet-phy at 1",
+		"motorcomm,tx-clk-adj-enabled", NULL},
+	{ "/soc/ethernet at 16040000/mdio/ethernet-phy at 1",
+		"motorcomm,tx-clk-100-inverted", NULL},
+	{"/soc/ethernet at 16040000/mdio/ethernet-phy at 1",
+		"motorcomm,rx-clk-drv-microamp", "3970"},
+	{"/soc/ethernet at 16040000/mdio/ethernet-phy at 1",
+		"motorcomm,rx-data-drv-microamp", "2910"},
+	{"/soc/ethernet at 16040000/mdio/ethernet-phy at 1",
+		"rx-internal-delay-ps", "0"},
+	{"/soc/ethernet at 16040000/mdio/ethernet-phy at 1",
+		"tx-internal-delay-ps", "0"},
+};
+
 void spl_fdt_fixup_mars(void *fdt)
 {
 	static const char compat[] = "milkv,mars\0starfive,jh7110";
@@ -226,6 +259,56 @@ void spl_fdt_fixup_version_b(void *fdt)
 	}
 }
 
+void spl_fdt_fixup_star64(void *fdt)
+{
+	static const char compat[] = "pine64,star64\0starfive,jh7110";
+	u32 phandle;
+	u8 i;
+	int offset;
+	int ret;
+
+	fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat));
+	fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model",
+			   "Pine64 Star64");
+
+	/* gmac0 */
+	offset = fdt_path_offset(fdt, "/soc/clock-controller at 17000000");
+	phandle = fdt_get_phandle(fdt, offset);
+	offset = fdt_path_offset(fdt, "/soc/ethernet at 16030000");
+
+	fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
+	fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX);
+	fdt_setprop_u32(fdt, offset,  "assigned-clock-parents", phandle);
+	fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents",
+			   JH7110_AONCLK_GMAC0_RMII_RTX);
+
+	/* gmac1 */
+	offset = fdt_path_offset(fdt, "/soc/clock-controller at 13020000");
+	phandle = fdt_get_phandle(fdt, offset);
+	offset = fdt_path_offset(fdt, "/soc/ethernet at 16040000");
+
+	fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle);
+	fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX);
+	fdt_setprop_u32(fdt, offset,  "assigned-clock-parents", phandle);
+	fdt_appendprop_u32(fdt, offset,  "assigned-clock-parents",
+			   JH7110_SYSCLK_GMAC1_RMII_RTX);
+
+	for (i = 0; i < ARRAY_SIZE(star64_pine64); i++) {
+		offset = fdt_path_offset(fdt, star64_pine64[i].path);
+
+		if (star64_pine64[i].value)
+			ret = fdt_setprop_u32(fdt, offset,  star64_pine64[i].name,
+					      dectoul(star64_pine64[i].value, NULL));
+		else
+			ret = fdt_setprop_empty(fdt, offset, star64_pine64[i].name);
+
+		if (ret) {
+			pr_err("%s set prop %s fail.\n", __func__, star64_pine64[i].name);
+				break;
+		}
+	}
+}
+
 void spl_perform_fixups(struct spl_image_info *spl_image)
 {
 	u8 version;
@@ -252,6 +335,8 @@ void spl_perform_fixups(struct spl_image_info *spl_image)
 			spl_fdt_fixup_version_b(spl_image->fdt_addr);
 		break;
 		};
+	} else if (!strncmp(product_id, "STAR64", 6)) {
+		spl_fdt_fixup_star64(spl_image->fdt_addr);
 	} else {
 		pr_err("Unknown product %s\n", product_id);
 	};
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c
index a86bca533b..1e7c41f01b 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -23,6 +23,8 @@ DECLARE_GLOBAL_DATA_PTR;
 	"starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"
 #define FDTFILE_VISIONFIVE2_1_3B \
 	"starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
+#define FDTFILE_PINE64_STAR64 \
+	"starfive/jh7110-pine64-star64.dtb"
 
 /* enable U74-mc hart1~hart4 prefetcher */
 static void enable_prefetcher(void)
@@ -78,6 +80,8 @@ static void set_fdtfile(void)
 			fdtfile = FDTFILE_VISIONFIVE2_1_3B;
 			break;
 		}
+	} else if (!strncmp(product_id, "STAR64", 6)) {
+		fdtfile = FDTFILE_PINE64_STAR64;
 	} else {
 		log_err("Unknown product\n");
 		return;
-- 
2.44.0