[Agilex7 M-series Platform Enablement v1 13/16] ddr: altera: soc64: Fix dram size calculation in clamshell mode

[tingting.meng at intel.com]

From: Teik Heng Chong <teik.heng.chong at intel.com>

This patch is to fix wrong memory size calculation in clamshell mode

Signed-off-by: Teik Heng Chong <teik.heng.chong at intel.com>
Signed-off-by: Tingting Meng <tingting.meng at intel.com>
---
 drivers/ddr/altera/sdram_soc64.c | 16 +++++++++++++++-
 drivers/ddr/altera/sdram_soc64.h |  5 +++++
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index 8f2085f3a0..27580cce2f 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -27,6 +27,9 @@
 
 #define PGTABLE_OFF	0x4000
 
+#define SINGLE_RANK_CLAMSHELL	0xC3C3
+#define DUAL_RANK_CLAMSHELL	0xA5A5
+
 #if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
 u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg)
 {
@@ -240,8 +243,19 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat)
 {
 	u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
 
+	u32 reg_ctrlcfg6_value = hmc_readl(plat, CTRLCFG6);
+	u32 cs_rank = CTRLCFG6_CFG_CS_CHIP(reg_ctrlcfg6_value);
+	u32 cs_addr_width;
+
+	if (cs_rank == SINGLE_RANK_CLAMSHELL)
+		cs_addr_width = 0;
+	else if (cs_rank == DUAL_RANK_CLAMSHELL)
+		cs_addr_width = 1;
+	else
+		cs_addr_width = DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw);
+
 	phys_size_t size = (phys_size_t)1 <<
-			(DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
+			(cs_addr_width +
 			 DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
 			 DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 			 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
index add7df01a5..8b3b53cf5d 100644
--- a/drivers/ddr/altera/sdram_soc64.h
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -78,6 +78,8 @@ struct altera_sdram_plat {
 #define CTRLCFG0			0x28
 #define CTRLCFG1			0x2c
 #define CTRLCFG3                        0x34
+#define CTRLCFG5                        0x3c
+#define CTRLCFG6                        0x40
 #define DRAMTIMING0			0x50
 #define CALTIMING0			0x7c
 #define CALTIMING1			0x80
@@ -118,6 +120,9 @@ struct altera_sdram_plat {
 #define CTRLCFG1_CFG_CTRL_EN_ECC(x)			\
 	(((x) >> 7) & 0x1)
 
+#define CTRLCFG6_CFG_CS_CHIP(x)				\
+	((x) & 0xFFFF)
+
 #define DRAMTIMING0_CFG_TCL(x)				\
 	((x) & 0x7F)
 
-- 
2.25.1