[PATCH 2/2] usb: dwc2: Update reset method for host and device mode
Kongyang Liu
seashell11234455 at gmail.com
Wed May 22 16:22:49 CEST 2024
Starting from version 4.20a, there has been a change in the reset method.
A new bit, GRSTCTL_CSFTRST_DONE, has been introduced in the GRSTCTL
register to indicate whether the reset has been completed.
This patch mainly refers to the patch in the kernel.
Link: https://lore.kernel.org/all/9be2bb0c728da3dabf634c894f77e0e9709edeaa.1590040892.git.hminas@synopsys.com/
Signed-off-by: Kongyang Liu <seashell11234455 at gmail.com>
---
drivers/usb/common/dwc2_core.c | 50 +++++++++++++++++++++++++++++++
drivers/usb/common/dwc2_core.h | 1 +
drivers/usb/gadget/dwc2_udc_otg.c | 2 +-
drivers/usb/host/dwc2.c | 36 ++--------------------
4 files changed, 55 insertions(+), 34 deletions(-)
diff --git a/drivers/usb/common/dwc2_core.c b/drivers/usb/common/dwc2_core.c
index 2fa11fd59d..323326e05d 100644
--- a/drivers/usb/common/dwc2_core.c
+++ b/drivers/usb/common/dwc2_core.c
@@ -10,6 +10,56 @@
#include "dwc2_core.h"
+int dwc2_core_reset(struct dwc2_core_regs *regs)
+{
+ u32 snpsid;
+ int ret;
+ bool host_mode = false;
+
+ if (!(readl(®s->global_regs.gotgctl) & GOTGCTL_CONID_B) ||
+ (readl(®s->global_regs.gusbcfg) & GUSBCFG_FORCEDEVMODE))
+ host_mode = true;
+
+ /* Core Soft Reset */
+ snpsid = readl(®s->global_regs.gsnpsid);
+ writel(GRSTCTL_CSFTRST, ®s->global_regs.grstctl);
+ if (FIELD_GET(GSNPSID_VER_MASK, snpsid) < 0x420a) {
+ ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_CSFTRST,
+ false, 1000, false);
+ if (ret) {
+ log_warning("%s: Waiting for GRSTCTL_CSFTRST timeout\n", __func__);
+ return -EBUSY;
+ }
+ } else {
+ ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_CSFTRST_DONE,
+ true, 1000, false);
+ if (ret) {
+ log_warning("%s: Waiting for GRSTCTL_CSFTRST_DONE timeout\n", __func__);
+ return -EBUSY;
+ }
+ clrsetbits_le32(®s->global_regs.grstctl, GRSTCTL_CSFTRST, GRSTCTL_CSFTRST_DONE);
+ }
+
+ /* Wait for AHB master IDLE state. */
+ ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_AHBIDLE,
+ true, 1000, false);
+ if (ret) {
+ log_warning("%s: Waiting for GRSTCTL_AHBIDLE timeout\n", __func__);
+ return -EBUSY;
+ }
+
+ if (host_mode) {
+ ret = wait_for_bit_le32(®s->global_regs.gintsts, GINTSTS_CURMODE_HOST,
+ host_mode, 1000, false);
+ if (ret) {
+ log_warning("%s: Waiting for GINTSTS_CURMODE_HOST timeout\n", __func__);
+ return -EBUSY;
+ }
+ }
+
+ return 0;
+}
+
void dwc2_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
{
int ret;
diff --git a/drivers/usb/common/dwc2_core.h b/drivers/usb/common/dwc2_core.h
index 8303153446..dd6937dd30 100644
--- a/drivers/usb/common/dwc2_core.h
+++ b/drivers/usb/common/dwc2_core.h
@@ -123,6 +123,7 @@ struct dwc2_core_regs {
u8 ep_fifo[16][0x1000];
};
+int dwc2_core_reset(struct dwc2_core_regs *regs);
void dwc2_flush_tx_fifo(struct dwc2_core_regs *regs, const int num);
void dwc2_flush_rx_fifo(struct dwc2_core_regs *regs);
diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c
index ac902b325a..727832e859 100644
--- a/drivers/usb/gadget/dwc2_udc_otg.c
+++ b/drivers/usb/gadget/dwc2_udc_otg.c
@@ -469,7 +469,7 @@ static void reconfig_usbd(struct dwc2_udc *dev)
u32 max_hw_ep;
int pdata_hw_ep;
- writel(GRSTCTL_CSFTRST, ®->global_regs.grstctl);
+ dwc2_core_reset(reg);
debug("Resetting OTG controller\n");
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 93ed9604c2..6e73a3d90d 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -109,36 +109,6 @@ static void init_fslspclksel(struct dwc2_core_regs *regs)
FIELD_PREP(HCFG_FSLSPCLKSEL_MASK, phyclk));
}
-/*
- * Do core a soft reset of the core. Be careful with this because it
- * resets all the internal state machines of the core.
- */
-static void dwc_otg_core_reset(struct udevice *dev,
- struct dwc2_core_regs *regs)
-{
- int ret;
-
- /* Wait for AHB master IDLE state. */
- ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_AHBIDLE,
- true, 1000, false);
- if (ret)
- dev_info(dev, "%s: Timeout!\n", __func__);
-
- /* Core Soft Reset */
- writel(GRSTCTL_CSFTRST, ®s->global_regs.grstctl);
- ret = wait_for_bit_le32(®s->global_regs.grstctl, GRSTCTL_CSFTRST,
- false, 1000, false);
- if (ret)
- dev_info(dev, "%s: Timeout!\n", __func__);
-
- /*
- * Wait for core to come out of reset.
- * NOTE: This long sleep is _very_ important, otherwise the core will
- * not stay in host mode after a connector ID change!
- */
- mdelay(100);
-}
-
#if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR)
static int dwc_vbus_supply_init(struct udevice *dev)
{
@@ -311,7 +281,7 @@ static void dwc_otg_core_init(struct udevice *dev)
writel(usbcfg, ®s->global_regs.gusbcfg);
/* Reset the Controller */
- dwc_otg_core_reset(dev, regs);
+ dwc2_core_reset(regs);
/*
* This programming sequence needs to happen in FS mode before
@@ -323,7 +293,7 @@ static void dwc_otg_core_init(struct udevice *dev)
setbits_le32(®s->global_regs.gusbcfg, GUSBCFG_PHYSEL);
/* Reset after a PHY select */
- dwc_otg_core_reset(dev, regs);
+ dwc2_core_reset(regs);
/*
* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
@@ -369,7 +339,7 @@ static void dwc_otg_core_init(struct udevice *dev)
writel(usbcfg, ®s->global_regs.gusbcfg);
/* Reset after setting the PHY parameters */
- dwc_otg_core_reset(dev, regs);
+ dwc2_core_reset(regs);
#endif
usbcfg = readl(®s->global_regs.gusbcfg);
--
2.41.0
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