[PATCH 2/4] clk: sophgo: cv1800b: Add clock controller driver for cv1800b SoC

[Yixun Lan]

Hi Kongyang:

I've got one compiling error

On 23:07 Sun 19 May     , Kongyang Liu wrote:
> Add clock controller driver for sophgo cv1800b SoC
> 
> Signed-off-by: Kongyang Liu <seashell11234455 at gmail.com>
> ---
> 
>  drivers/clk/Kconfig              |   1 +
>  drivers/clk/Makefile             |   1 +
>  drivers/clk/sophgo/Kconfig       |  14 +
>  drivers/clk/sophgo/Makefile      |   6 +
>  drivers/clk/sophgo/clk-common.h  |  74 +++
>  drivers/clk/sophgo/clk-cv1800b.c | 794 +++++++++++++++++++++++++++++++
>  drivers/clk/sophgo/clk-cv1800b.h | 123 +++++
>  drivers/clk/sophgo/clk-ip.c      | 594 +++++++++++++++++++++++
>  drivers/clk/sophgo/clk-ip.h      | 288 +++++++++++
>  drivers/clk/sophgo/clk-pll.c     | 284 +++++++++++
>  drivers/clk/sophgo/clk-pll.h     |  74 +++
>  11 files changed, 2253 insertions(+)
>  create mode 100644 drivers/clk/sophgo/Kconfig
>  create mode 100644 drivers/clk/sophgo/Makefile
>  create mode 100644 drivers/clk/sophgo/clk-common.h
>  create mode 100644 drivers/clk/sophgo/clk-cv1800b.c
>  create mode 100644 drivers/clk/sophgo/clk-cv1800b.h
>  create mode 100644 drivers/clk/sophgo/clk-ip.c
>  create mode 100644 drivers/clk/sophgo/clk-ip.h
>  create mode 100644 drivers/clk/sophgo/clk-pll.c
>  create mode 100644 drivers/clk/sophgo/clk-pll.h
> 

...

> +static ulong cv1800b_ipll_set_rate(struct clk *clk, ulong rate)
> +{
> +	struct cv1800b_clk_ipll *pll = to_clk_ipll(clk);
> +	ulong parent_rate = clk_get_parent_rate(clk);
> +	u32 pre_div, post_div, div;
> +	u32 pre_div_sel, post_div_sel, div_sel;
> +	ulong new_rate, best_rate = 0;
> +	u32 mode, ictrl;
> +	u32 test, val;
> +
> +	FOR_RANGE(pre_div, PLL_PRE_DIV)
> +	{
> +		FOR_RANGE(post_div, PLL_POST_DIV)
> +		{
> +			FOR_RANGE(div, PLL_DIV)
> +			{
> +				new_rate = DIV_ROUND_DOWN_ULL(parent_rate * div
                                                                          ~~~~~~
							     miss a comma here
> +							      pre_div * post_div);
> +				if (rate - new_rate < rate - best_rate) {
> +					best_rate = new_rate;
> +					pre_div_sel = pre_div;
> +					post_div_sel = post_div;
> +					div_sel = div;
> +				}
> +			}
> +		}
> +	}
> +
> +	FOR_RANGE(mode, PLL_MODE)

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55