[PATCH] riscv: dts: jh7110: Update qspi node with upstream

[Heinrich Schuchardt]

On 27.05.24 12:47, matthias.bgg at kernel.org wrote:
> From: Matthias Brugger <mbrugger at suse.com>
> 
> Upstream node uses a specific SoC compatible to make the kernel driver
> work. Copy over the upstream node to fullfill that need.

Thanks for looking into the compatibility of the U-Boot device-tree with 
Linux.

Could you, please, replace "Upstream" by "Linux" and refer to the 
relevant file:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/riscv/boot/dts/starfive/jh7110-common.dtsi?h=v6.10-rc1

%s/fullfill/fulfill/

Please, fully describe the change, e.g.

* Define MTD partitions for StarFive VisionFive 2
* Adjust QSPI compatible string to use StarFive specific driver
* Adjust QSPI clock and reset definitions

> 
> Signed-off-by: Matthias Brugger <mbrugger at suse.com>
> ---
> 
>   .../jh7110-starfive-visionfive-2-u-boot.dtsi  |  2 +-
>   .../dts/jh7110-starfive-visionfive-2.dtsi     | 29 ++++++++++++++++---
>   arch/riscv/dts/jh7110.dtsi                    | 19 +++++++-----
>   3 files changed, 37 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> index 3012466b305..a69d8fcb391 100644
> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> @@ -40,7 +40,7 @@
>   &qspi {
>   	bootph-pre-ram;
>   
> -	nor-flash at 0 {
> +	nor_flash at 0 {
>   		bootph-pre-ram;
>   	};
>   };
> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> index e11babc1cde..375449b73a8 100644
> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> @@ -305,17 +305,38 @@
>   };
>   
>   &qspi {
> -	spi-max-frequency = <250000000>;
> +	#address-cells = <1>;
> +	#size-cells = <0>;
>   	status = "okay";
>   
> -	nor-flash at 0 {
> +	nor_flash: nor_flash at 0 {
>   		compatible = "jedec,spi-nor";
> -		reg=<0>;
> -		spi-max-frequency = <100000000>;
> +		reg = <0>;
> +		cdns,read-delay = <5>;
> +		spi-max-frequency = <12000000>;
>   		cdns,tshsl-ns = <1>;
>   		cdns,tsd2d-ns = <1>;
>   		cdns,tchsh-ns = <1>;
>   		cdns,tslch-ns = <1>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			spl at 0 {
> +				reg = <0x0 0x80000>;
> +			};

Why should we have a gap here?

%s/0x80000/0xf0000/

> +			uboot-env at f0000 {
> +				reg = <0xf0000 0x10000>;
> +			};
> +			uboot at 100000 {
> +				reg = <0x100000 0x400000>;
> +			};

And another gap here?

> +			reserved-data at 600000 {
> +				reg = <0x600000 0xa00000>;
> +			};

When replacing u-boot.itb by EDK II it would be preferable to have a 
single partition reaching to the end of the SPI-flash.

So I would suggest

uboot at 100000 {
	ret = <0x100000 0xf00000>;
}

Best regards

Heinrich

> +		};
>   	};
>   };
>   
> diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
> index 2cdc683d49b..2b331e58497 100644
> --- a/arch/riscv/dts/jh7110.dtsi
> +++ b/arch/riscv/dts/jh7110.dtsi
> @@ -480,19 +480,22 @@
>   		};
>   
>   		qspi: spi at 13010000 {
> -			compatible = "cdns,qspi-nor";
> -			reg = <0x0 0x13010000 0x0 0x10000
> -				0x0 0x21000000 0x0 0x400000>;
> -			clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>;
> -			clock-names = "clk_ref";
> +			compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
> +			reg = <0x0 0x13010000 0x0 0x10000>,
> +			      <0x0 0x21000000 0x0 0x400000>;
> +			interrupts = <25>;
> +			clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
> +				 <&syscrg JH7110_SYSCLK_QSPI_AHB>,
> +				 <&syscrg JH7110_SYSCLK_QSPI_APB>;
> +			clock-names = "ref", "ahb", "apb";
>   			resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
>   				 <&syscrg JH7110_SYSRST_QSPI_AHB>,
>   				 <&syscrg JH7110_SYSRST_QSPI_REF>;
> -			reset-names = "rst_apb", "rst_ahb", "rst_ref";
> +			reset-names = "qspi", "qspi-ocp", "rstc_ref";
>   			cdns,fifo-depth = <256>;
>   			cdns,fifo-width = <4>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> +			cdns,trigger-address = <0x0>;
> +			status = "disabled";
>   		};
>   
>   		syscrg: clock-controller at 13020000 {