[PATCH RFC v2 22/23] sysreset: rockchip: use fst reset for ARM64 SOC

[Jonas Karlman]

Hi Anand and Kever,

On 2024-05-31 16:18, Anand Moon wrote:
> From: Kever Yang <kever.yang at rock-chips.com>
> 
> Rockchip ARM64 SOC will change cpu entry, only fst reset can reset it.

What is this trying to fix? And what SoCs is affected?

My arm64 RK SoCs seem to reset using warm reset (second global reset).

> 
> Cc: Jagan Teki <jagan at edgeble.ai>
> Signed-off-by: Kever Yang <kever.yang at rock-chips.com>
> ---
>  drivers/sysreset/sysreset_rockchip.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c
> index f353f9b4c7..17aa191349 100644
> --- a/drivers/sysreset/sysreset_rockchip.c
> +++ b/drivers/sysreset/sysreset_rockchip.c
> @@ -22,7 +22,12 @@ int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type)
>  
>  	switch (type) {
>  	case SYSRESET_WARM:
> +#ifdef CONFIG_ARM64
> +		/* Rockchip 64bit SOC need fst reset for cpu reset entry */
> +		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);
> +#else
>  		writel(0xeca8, cru_base + offset->glb_srst_snd_value);
> +#endif

If this is needed maybe use something like this and let it fall through
to SYSRESET_COLD?

  if (!IS_ENABLED(CONFIG_ARM64)) {
	writel(0xeca8, cru_base + offset->glb_srst_snd_value);
	break;
  }

Regards,
Jonas

>  		break;
>  	case SYSRESET_COLD:
>  		writel(0xfdb9, cru_base + offset->glb_srst_fst_value);