[PATCH] riscv: Introduce configuration for 64bit version Microblaze V
Begari, Padmarao
Padmarao.Begari at amd.com
Thu Nov 7 05:20:20 CET 2024
> From: Simek, Michal <michal.simek at amd.com>
> Sent: Friday, November 1, 2024 3:21 PM
> To: u-boot at lists.denx.de; git at xilinx.com
> Cc: Chia-Wei Wang <chiawei_wang at aspeedtech.com>; Conor Dooley
> <conor.dooley at microchip.com>; Kongyang Liu <seashell11234455 at gmail.com>;
> Leo <ycliang at andestech.com>; Marek Vasut <marex at denx.de>; Begari,
> Padmarao <Padmarao.Begari at amd.com>; Rick Chen <rick at andestech.com>;
> Sumit Garg <sumit.garg at linaro.org>; Tom Rini <trini at konsulko.com>
> Subject: [PATCH] riscv: Introduce configuration for 64bit version Microblaze V
>
> The commit 7576ab2facae ("riscv: Add support for AMD/Xilinx MicroBlaze V")
> added support for 32bit version. 64bit version is also available that's why wire it up
> too.
> DT is providing description for generic QEMU target.
>
> Signed-off-by: Michal Simek <michal.simek at amd.com>
Reviewed-by: Padmarao Begari <padmarao.begari at amd.com>
> ---
>
> arch/riscv/dts/Makefile | 1 +
> arch/riscv/dts/xilinx-mbv64.dts | 99 ++++++++++++++++++++++++++++
> configs/xilinx_mbv64_defconfig | 44 +++++++++++++
> configs/xilinx_mbv64_smode_defconfig | 48 ++++++++++++++
> 4 files changed, 192 insertions(+)
> create mode 100644 arch/riscv/dts/xilinx-mbv64.dts create mode 100644
> configs/xilinx_mbv64_defconfig create mode 100644
> configs/xilinx_mbv64_smode_defconfig
>
> diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index
> bf32ead01b03..de356584bf1e 100644
> --- a/arch/riscv/dts/Makefile
> +++ b/arch/riscv/dts/Makefile
> @@ -10,6 +10,7 @@ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-
> bit.dtb
> dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-
> visionfive-2.dtb
> dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
> dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
> +dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb
> dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb
>
> include $(srctree)/scripts/Makefile.dts diff --git a/arch/riscv/dts/xilinx-mbv64.dts
> b/arch/riscv/dts/xilinx-mbv64.dts new file mode 100644 index
> 000000000000..4d65d338ecb6
> --- /dev/null
> +++ b/arch/riscv/dts/xilinx-mbv64.dts
> @@ -0,0 +1,99 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * dts file for AMD MicroBlaze V
> + *
> + * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
> + *
> + * Michal Simek <michal.simek at amd.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "binman.dtsi"
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + model = "AMD MicroBlaze V 64bit";
> + compatible = "qemu,mbv", "amd,mbv";
> +
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <100000000>;
> + cpu_0: cpu at 0 {
> + compatible = "amd,mbv64", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + riscv,isa = "rv64imafdc";
> + i-cache-size = <32768>;
> + d-cache-size = <32768>;
> + clock-frequency = <100000000>;
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + bootargs = "earlycon";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory at 80000000 {
> + device_type = "memory";
> + reg = <0 0x80000000 0 0x40000000>;
> + };
> +
> + clk100: clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + axi: axi {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> + bootph-all;
> +
> + axi_intc: interrupt-controller at 41200000 {
> + compatible = "xlnx,xps-intc-1.00.a";
> + reg = <0 0x41200000 0 0x1000>;
> + interrupt-controller;
> + interrupt-parent = <&cpu0_intc>;
> + #interrupt-cells = <2>;
> + kind-of-intr = <0>;
> + };
> +
> + xlnx_timer0: timer at 41c00000 {
> + compatible = "xlnx,xps-timer-1.00.a";
> + reg = <0 0x41c00000 0 0x1000>;
> + interrupt-parent = <&axi_intc>;
> + interrupts = <0 2>;
> + bootph-all;
> + xlnx,one-timer-only = <0>;
> + clock-names = "s_axi_aclk";
> + clocks = <&clk100>;
> + };
> +
> + uart0: serial at 40600000 {
> + compatible = "xlnx,xps-uartlite-1.00.a";
> + reg = <0 0x40600000 0 0x1000>;
> + interrupt-parent = <&axi_intc>;
> + interrupts = <1 2>;
> + bootph-all;
> + clocks = <&clk100>;
> + current-speed = <115200>;
> + xlnx,data-bits = <8>;
> + xlnx,use-parity = <0>;
> + };
> + };
> +};
> diff --git a/configs/xilinx_mbv64_defconfig b/configs/xilinx_mbv64_defconfig new file
> mode 100644 index 000000000000..aad9c3f140b2
> --- /dev/null
> +++ b/configs/xilinx_mbv64_defconfig
> @@ -0,0 +1,44 @@
> +CONFIG_RISCV=y
> +CONFIG_SYS_MALLOC_LEN=0xe00000
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
> +CONFIG_ENV_SIZE=0x20000
> +CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv64"
> +CONFIG_SPL_STACK=0x80200000
> +CONFIG_SPL_BSS_START_ADDR=0x84000000
> +CONFIG_SPL_BSS_MAX_SIZE=0x80000
> +CONFIG_SYS_LOAD_ADDR=0x80200000
> +CONFIG_SPL_SIZE_LIMIT=0x40000
> +CONFIG_SPL=y
> +CONFIG_DEBUG_UART_BASE=0x40600000
> +CONFIG_DEBUG_UART_CLOCK=100000000
> +CONFIG_SYS_CLK_FREQ=100000000
> +CONFIG_BOOT_SCRIPT_OFFSET=0x0
> +CONFIG_DEBUG_UART=y
> +CONFIG_TARGET_XILINX_MBV=y
> +CONFIG_ARCH_RV64I=y
> +# CONFIG_SPL_SMP is not set
> +CONFIG_REMAKE_ELF=y
> +CONFIG_FIT=y
> +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_DISPLAY_CPUINFO=y
> +CONFIG_DISPLAY_BOARDINFO=y
> +# CONFIG_BOARD_LATE_INIT is not set
> +CONFIG_SPL_MAX_SIZE=0x40000
> +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
> CONFIG_SPL_SYS_MALLOC=y
> +CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
> +# CONFIG_CMD_MII is not set
> +CONFIG_CMD_TIMER=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_DM_MTD=y
> +CONFIG_DEBUG_UART_ANNOUNCE=y
> +CONFIG_DEBUG_UART_SKIP_INIT=y
> +CONFIG_XILINX_UARTLITE=y
> +CONFIG_XILINX_TIMER=y
> +# CONFIG_BINMAN_FDT is not set
> +CONFIG_PANIC_HANG=y
> +CONFIG_SPL_GZIP=y
> diff --git a/configs/xilinx_mbv64_smode_defconfig
> b/configs/xilinx_mbv64_smode_defconfig
> new file mode 100644
> index 000000000000..628e0ed5be2c
> --- /dev/null
> +++ b/configs/xilinx_mbv64_smode_defconfig
> @@ -0,0 +1,48 @@
> +CONFIG_RISCV=y
> +CONFIG_SYS_MALLOC_LEN=0xe00000
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
> +CONFIG_ENV_SIZE=0x20000
> +CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv64"
> +CONFIG_SPL_STACK=0x80200000
> +CONFIG_SPL_BSS_START_ADDR=0x84000000
> +CONFIG_SPL_BSS_MAX_SIZE=0x80000
> +CONFIG_SYS_LOAD_ADDR=0x80200000
> +CONFIG_SPL_SIZE_LIMIT=0x40000
> +CONFIG_SPL=y
> +CONFIG_DEBUG_UART_BASE=0x40600000
> +CONFIG_DEBUG_UART_CLOCK=1000000
> +CONFIG_SYS_CLK_FREQ=100000000
> +CONFIG_BOOT_SCRIPT_OFFSET=0x0
> +CONFIG_TARGET_XILINX_MBV=y
> +CONFIG_SPL_OPENSBI_LOAD_ADDR=0x80100000
> +CONFIG_ARCH_RV64I=y
> +CONFIG_RISCV_SMODE=y
> +# CONFIG_SPL_SMP is not set
> +CONFIG_REMAKE_ELF=y
> +CONFIG_FIT=y
> +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_DISPLAY_CPUINFO=y
> +CONFIG_DISPLAY_BOARDINFO=y
> +# CONFIG_BOARD_LATE_INIT is not set
> +CONFIG_SPL_MAX_SIZE=0x40000
> +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
> CONFIG_SPL_SYS_MALLOC=y
> +CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
> +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
> +# CONFIG_CMD_MII is not set
> +CONFIG_CMD_TIMER=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_DM_MTD=y
> +CONFIG_DEBUG_UART_UARTLITE=y
> +CONFIG_DEBUG_UART_ANNOUNCE=y
> +CONFIG_DEBUG_UART_SKIP_INIT=y
> +CONFIG_XILINX_UARTLITE=y
> +# CONFIG_RISCV_TIMER is not set
> +CONFIG_XILINX_TIMER=y
> +# CONFIG_BINMAN_FDT is not set
> +CONFIG_PANIC_HANG=y
> +CONFIG_SPL_GZIP=y
> --
> 2.43.0
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