[PATCH v4 1/5] arm: dts: k3-j7200-r5-common: Add msmc clk to a72 node

[Manorit Chawdhry]

Hi Aniket,

On 06:02-20241119, Aniket Limaye wrote:
> From: Reid Tonking <reidt at ti.com>
> 
> The j7200 SOC has a single DDR controller and hence no need for
> configuring the MSMC interleaver. Hence we do not have an explicit node
> for MSMC in j7200 DT, unlike j721s2/j784s4.
> 
> Also, MSMC clk id is described under A72SS0_CORE0 Device in TISCI
> documentation [0].
> 
> Considering the above, define the MSMC clk in the a72 node.
> 
> [0]: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html#clocks-for-a72ss0-core0-device
> 
> Signed-off-by: Reid Tonking <reidt at ti.com>
> ---
[..]
> ---
>  arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
> index f096b102793..06fffe2a11b 100644
> --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
> +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
> @@ -23,11 +23,12 @@
>  				<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
>  				<&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
>  		resets = <&k3_reset 202 0>;
> -		clocks = <&k3_clks 61 1>, <&k3_clks 202 2>;
> -		clock-names = "gtc", "core";
> -		assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 323 0>;
> -		assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>;
> -		assigned-clock-rates = <2000000000>, <200000000>;
> +		clocks = <&k3_clks 61 1>, <&k3_clks 202 2>, <&k3_clks 4 1> ;
> +		clock-names = "gtc", "core", "msmc";
> +		assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, <&k3_clks 4 1>,
> +						  <&k3_clks 323 0>;
> +		assigned-clock-parents= <0>, <0>, <0>, <&k3_clks 323 2>;
> +		assigned-clock-rates = <2000000000>, <200000000>, <1000000000>;

Reviewed-by: Manorit Chawdhry <m-chawdhry at ti.com>

Regards,
Manorit

>  		ti,sci = <&dmsc>;
>  		ti,sci-proc-id = <32>;
>  		ti,sci-host-id = <10>;
> -- 
> 2.47.0
>