[PATCH v4 2/3] board: phytec: imx93: Add eeprom-based hardware introspection

[Stefan Wahren]

Hi Christoph,

Am 20.11.24 um 17:31 schrieb Christoph Stoidner:
> The phyCORE-i.MX 93 is available in various variants. Relevant variant
> options for the spl/u-boot are:
> - with or without HS400 support for the eMMC
> - with 1GB ram chip, or 2GB ram chip
>
> The phyCORE's eeprom contains all information about the existing variant
> options. Add evaluation of the eeprom data to the spl/u-boot to
> enable/disable HS400 and to select the appropriate ram configuration at
> startup.
>
> Signed-off-by: Christoph Stoidner <c.stoidner at phytec.de>
> Reviewed-by: Wadim Egorov <w.egorov at phytec.de>
> Reviewed-by: Yannic Moog <y.moog at phytec.de>
> ---
> Cc: Mathieu Othacehe <m.othacehe at gmail.com>
> Cc: Christoph Stoidner <c.stoidner at phytec.de>
> Cc: Stefano Babic <sbabic at denx.de>
> Cc: Fabio Estevam <festevam at gmail.com>
> Cc: "NXP i.MX U-Boot Team" <uboot-imx at nxp.com>
> Cc: Tom Rini <trini at konsulko.com>
> Cc: Yannic Moog <y.moog at phytec.de>
> Cc: Primoz Fiser <primoz.fiser at norik.com>
> Cc: Andrej Picej <andrej.picej at norik.com>
> Cc: Wadim Egorov <w.egorov at phytec.de>
> ---
> Changes in v4:
> - add missing pinctrls for eMMC 100mhz and 200mhz
>
> Changes in v3:
> - remove unwanted dts node eepromid
> - correct typo in doc (PHYTEC_IMX93_VOLTAGE_3V3)
> - improve enum code-style (phytec_imx93_option_index)
>
> Changes in v2:
> - encapsulate handling of feature flag VOLTAGE into own function
> - move definition of enum phytec_imx93_ddr_eeprom_code into header file
>
>   arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi |  58 +++++++++
>   arch/arm/mach-imx/imx9/Kconfig                |   2 +
>   arch/arm/mach-imx/imx9/soc.c                  |   2 +-
>   board/phytec/common/Kconfig                   |   8 ++
>   board/phytec/common/Makefile                  |   1 +
>   board/phytec/common/imx93_som_detection.c     | 111 ++++++++++++++++++
>   board/phytec/common/imx93_som_detection.h     |  51 ++++++++
>   board/phytec/phycore_imx93/Kconfig            |  28 +++++
>   board/phytec/phycore_imx93/MAINTAINERS        |   5 +-
>   board/phytec/phycore_imx93/phycore-imx93.c    |  51 ++++++++
>   board/phytec/phycore_imx93/spl.c              |  48 ++++++++
>   11 files changed, 363 insertions(+), 2 deletions(-)
>   create mode 100644 board/phytec/common/imx93_som_detection.c
>   create mode 100644 board/phytec/common/imx93_som_detection.h
>
> diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
> index 6897c91f4d..702d86f4e0 100644
> --- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
> +++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
> @@ -139,6 +139,13 @@
>   &usdhc1 {
>   	bootph-pre-ram;
>   	bootph-some-ram;
> +	/*
> +	 * Remove pinctrl assignments once they are added to imx93-phycore-som.dtsi
> +	 */
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc1>;
> +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>   };
>
>   &usdhc2 {
> @@ -215,6 +222,48 @@
>   			MX93_PAD_ENET2_RD3__GPIO4_IO27			0x31e
>   		>;
>   	};
> +
> +	/*
> +	 * Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz once they
> +	 * are added to imx93-phycore-som.dtsi
> +	 */
> +	/* need to config the SION for data and cmd pad, refer to ERR052021 */
> +	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> +		bootph-pre-ram;
> +		bootph-some-ram;
> +		fsl,pins = <
> +			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
> +			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e
> +			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000138e
> +			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x4000139e
> +			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be
Could you please explain why the pin configuration for 100 MHz of DATA0
& DATA2 is different from the other data pins?
> +			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x4000139e
> +			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x4000139e
> +			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x4000139e
> +			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x4000139e
> +			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x4000139e
> +			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
> +		>;
> +	};
> +
> +	/* need to config the SION for data and cmd pad, refer to ERR052021 */
> +	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> +		bootph-pre-ram;
> +		bootph-some-ram;
> +		fsl,pins = <
> +			MX93_PAD_SD1_CLK__USDHC1_CLK		0x17be
> +			MX93_PAD_SD1_CMD__USDHC1_CMD		0x4000139e
> +			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x4000139e
> +			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x400013be
> +			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x400013be
> +			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x400013be
> +			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x400013be
> +			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x400013be
> +			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x400013be
> +			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x400013be
> +			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
> +		>;
> +	};
>   };
>