[PATCH v4 2/3] board: phytec: imx93: Add eeprom-based hardware introspection
Stefan Wahren
wahrenst at gmx.net
Mon Nov 25 10:39:19 CET 2024
Hi Christoph,
Am 25.11.24 um 09:28 schrieb Christoph Stoidner:
> Hi Stefan,
>
> On Do, 2024-11-21 at 11:12 +0100, Stefan Wahren wrote:
>> Hi Christoph,
>>
>> Am 20.11.24 um 17:31 schrieb Christoph Stoidner:
>>
> [...]
>
>>> diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
>>> b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
>>> index 6897c91f4d..702d86f4e0 100644
>>> --- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
>>> +++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi
>>> @@ -139,6 +139,13 @@
>>> &usdhc1 {
>>> bootph-pre-ram;
>>> bootph-some-ram;
>>> + /*
>>> + * Remove pinctrl assignments once they are added to imx93-
>>> phycore-som.dtsi
>>> + */
>>> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
>>> + pinctrl-0 = <&pinctrl_usdhc1>;
>>> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
>>> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>>> };
>>>
>>> &usdhc2 {
>>> @@ -215,6 +222,48 @@
>>> MX93_PAD_ENET2_RD3__GPIO4_IO27
>>> 0x31e
>>> >;
>>> };
>>> +
>>> + /*
>>> + * Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz
>>> once they
>>> + * are added to imx93-phycore-som.dtsi
>>> + */
>>> + /* need to config the SION for data and cmd pad, refer to
>>> ERR052021 */
>>> + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
>>> + bootph-pre-ram;
>>> + bootph-some-ram;
>>> + fsl,pins = <
>>> + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1
>>> 7be
>>> + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4
>>> 000139e
>>> + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4
>>> 000138e
>>> + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4
>>> 000139e
>>> + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4
>>> 00013be
>> Could you please explain why the pin configuration for 100 MHz of
>> DATA0
>> & DATA2 is different from the other data pins?
> The difference in the values is due to different drive-strength
> settings per pin. The values are the result of measurements we
> did for the eMMC interface. There, we adjusted each pin's
> drive-strength to get it's best signal quality.
Thanks for the explanation. So you measured also the 200 MHz case?
Because there are no differences between the data pins.
Regards
>
> Regards,
> Christoph
>
>>> + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4
>>> 000139e
>>> + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4
>>> 000139e
>>> + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4
>>> 000139e
>>> + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4
>>> 000139e
>>> + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4
>>> 000139e
>>> + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1
>>> 79e
>>> + >;
>>> + };
>>> +
>>> + /* need to config the SION for data and cmd pad, refer to
>>> ERR052021 */
>>> + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
>>> + bootph-pre-ram;
>>> + bootph-some-ram;
>>> + fsl,pins = <
>>> + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1
>>> 7be
>>> + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4
>>> 000139e
>>> + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4
>>> 000139e
>>> + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4
>>> 00013be
>>> + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4
>>> 00013be
>>> + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4
>>> 00013be
>>> + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4
>>> 00013be
>>> + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4
>>> 00013be
>>> + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4
>>> 00013be
>>> + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4
>>> 00013be
>>> + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1
>>> 79e
>>> + >;
>>> + };
>>> };
>>>
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