[PATCH v6 04/11] riscv: dts: jh7110: Move common code to the new jh7110-common-u-boot.dtsi
E Shattow
lucent at gmail.com
Tue Nov 26 16:24:53 CET 2024
On Sun, Nov 24, 2024 at 4:33 PM Hal Feng <hal.feng at starfivetech.com> wrote:
>
> To support JH7110 based boards besides v1.3B,
> add a common dtsi and add common code to it.
>
> Tested-by: E Shattow <lucent at gmail.com>
> Signed-off-by: Hal Feng <hal.feng at starfivetech.com>
> ---
> arch/riscv/dts/jh7110-common-u-boot.dtsi | 144 ++++++++++++++++++
> ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 140 +----------------
> 2 files changed, 145 insertions(+), 139 deletions(-)
> create mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi
>
> diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi
> new file mode 100644
> index 0000000000..c44553455e
> --- /dev/null
> +++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi
> @@ -0,0 +1,144 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> + */
> +
> +#include "binman.dtsi"
> +#include "jh7110-u-boot.dtsi"
> +/ {
> + aliases {
> + spi0 = &qspi;
> + };
> +
> + chosen {
> + bootph-pre-ram;
> + };
> +
> + firmware {
> + spi0 = &qspi;
> + bootph-pre-ram;
> + };
> +
> + config {
> + bootph-pre-ram;
> + u-boot,spl-payload-offset = <0x100000>;
> + };
> +
> + memory at 40000000 {
> + bootph-pre-ram;
> + };
> +};
> +
> +&uart0 {
> + bootph-pre-ram;
> + reg-offset = <0>;
> + current-speed = <115200>;
> + clock-frequency = <24000000>;
> +};
> +
> +&mmc0 {
> + bootph-pre-ram;
> + compatible = "snps,dw-mshc";
> +};
> +
> +&mmc1 {
> + bootph-pre-ram;
> + compatible = "snps,dw-mshc";
> +};
Following this series being applied should be an enhancement to add
the U-Boot JH7110 MMC driver wrapper and factor out this override.
Okay for now.
> +
> +&qspi {
> + bootph-pre-ram;
> + spi-max-frequency = <250000000>;
> +
> + flash at 0 {
> + bootph-pre-ram;
> + /delete-property/ cdns,read-delay;
> + spi-max-frequency = <100000000>;
> + };
> +};
> +
> +&syscrg {
> + assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
> + <&syscrg JH7110_SYSCLK_BUS_ROOT>,
> + <&syscrg JH7110_SYSCLK_PERH_ROOT>,
> + <&syscrg JH7110_SYSCLK_QSPI_REF>;
> + assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
> + <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> + <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> + <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
> + assigned-clock-rates = <0>, <0>, <0>, <0>;
> +};
> +
> +&sysgpio {
> + bootph-pre-ram;
> +};
> +
> +&mmc0_pins {
> + bootph-pre-ram;
> + rst-pins {
> + bootph-pre-ram;
> + };
> +};
> +
> +&mmc1_pins {
> + bootph-pre-ram;
> + clk-pins {
> + bootph-pre-ram;
> + };
> +
> + mmc-pins {
> + bootph-pre-ram;
> + };
> +};
> +
> +&i2c5_pins {
> + bootph-pre-ram;
> + i2c-pins {
> + bootph-pre-ram;
> + };
> +};
> +
> +&i2c5 {
> + bootph-pre-ram;
> + eeprom at 50 {
> + bootph-pre-ram;
> + compatible = "atmel,24c04";
> + reg = <0x50>;
> + pagesize = <16>;
> + };
> +};
(repeating my comment from "[PATCH v6 02/11] riscv: dts: jh7110: Make
u-boot device trees adapting to upstream DT")
In some configurations with RTC there is a conflict in the addressing
with EEPROM, as in:
https://github.com/milkv-mars/mars-buildroot-sdk/commit/d381610c92827de01b25843786012351b3f35519
Okay to keep this for now, a conflict is the exception and not the
normal situation. Refactor this out of U-Boot when EEPROM node is sent
upstream to Linux.
> +
> +&binman {
> + itb {
> + fit {
> + images {
> + fdt-1 {
> + description = "NAME";
> + load = <0x40400000>;
> + compression = "none";
> +
> + uboot_fdt_blob: blob-ext {
> + filename = "u-boot.dtb";
> + };
> + };
> + };
> +
> + configurations {
> + conf-1 {
> + fdt = "fdt-1";
> + };
> + };
> + };
> + };
> +
> + spl-img {
> + filename = "spl/u-boot-spl.bin.normal.out";
> +
> + mkimage {
> + args = "-T sfspl";
> +
> + u-boot-spl {
> + };
> + };
> + };
> +};
> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
> index c44553455e..e6bc6630dc 100644
> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
> @@ -3,142 +3,4 @@
> * Copyright (C) 2023 StarFive Technology Co., Ltd.
> */
>
> -#include "binman.dtsi"
> -#include "jh7110-u-boot.dtsi"
> -/ {
> - aliases {
> - spi0 = &qspi;
> - };
> -
> - chosen {
> - bootph-pre-ram;
> - };
> -
> - firmware {
> - spi0 = &qspi;
> - bootph-pre-ram;
> - };
> -
> - config {
> - bootph-pre-ram;
> - u-boot,spl-payload-offset = <0x100000>;
> - };
> -
> - memory at 40000000 {
> - bootph-pre-ram;
> - };
> -};
> -
> -&uart0 {
> - bootph-pre-ram;
> - reg-offset = <0>;
> - current-speed = <115200>;
> - clock-frequency = <24000000>;
> -};
> -
> -&mmc0 {
> - bootph-pre-ram;
> - compatible = "snps,dw-mshc";
> -};
> -
> -&mmc1 {
> - bootph-pre-ram;
> - compatible = "snps,dw-mshc";
> -};
> -
> -&qspi {
> - bootph-pre-ram;
> - spi-max-frequency = <250000000>;
> -
> - flash at 0 {
> - bootph-pre-ram;
> - /delete-property/ cdns,read-delay;
> - spi-max-frequency = <100000000>;
> - };
> -};
> -
> -&syscrg {
> - assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
> - <&syscrg JH7110_SYSCLK_BUS_ROOT>,
> - <&syscrg JH7110_SYSCLK_PERH_ROOT>,
> - <&syscrg JH7110_SYSCLK_QSPI_REF>;
> - assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
> - <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> - <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> - <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
> - assigned-clock-rates = <0>, <0>, <0>, <0>;
> -};
> -
> -&sysgpio {
> - bootph-pre-ram;
> -};
> -
> -&mmc0_pins {
> - bootph-pre-ram;
> - rst-pins {
> - bootph-pre-ram;
> - };
> -};
> -
> -&mmc1_pins {
> - bootph-pre-ram;
> - clk-pins {
> - bootph-pre-ram;
> - };
> -
> - mmc-pins {
> - bootph-pre-ram;
> - };
> -};
> -
> -&i2c5_pins {
> - bootph-pre-ram;
> - i2c-pins {
> - bootph-pre-ram;
> - };
> -};
> -
> -&i2c5 {
> - bootph-pre-ram;
> - eeprom at 50 {
> - bootph-pre-ram;
> - compatible = "atmel,24c04";
> - reg = <0x50>;
> - pagesize = <16>;
> - };
> -};
> -
> -&binman {
> - itb {
> - fit {
> - images {
> - fdt-1 {
> - description = "NAME";
> - load = <0x40400000>;
> - compression = "none";
> -
> - uboot_fdt_blob: blob-ext {
> - filename = "u-boot.dtb";
> - };
> - };
> - };
> -
> - configurations {
> - conf-1 {
> - fdt = "fdt-1";
> - };
> - };
> - };
> - };
> -
> - spl-img {
> - filename = "spl/u-boot-spl.bin.normal.out";
> -
> - mkimage {
> - args = "-T sfspl";
> -
> - u-boot-spl {
> - };
> - };
> - };
> -};
> +#include "jh7110-common-u-boot.dtsi"
> --
> 2.43.2
>
Reviewed-by: E Shattow <lucent at gmail.com>
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