[PATCH] mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes

[Abbarapu, Venkatesh]

Hi Prasanth,

> -----Original Message-----
> From: Prasanth Mantena <p-mantena at ti.com>
> Sent: Tuesday, November 26, 2024 10:38 AM
> To: Abbarapu, Venkatesh <venkatesh.abbarapu at amd.com>
> Cc: u-boot at lists.denx.de; j-humphreys at ti.com; Simek, Michal
> <michal.simek at amd.com>; jagan at amarulasolutions.com; vigneshr at ti.com; u-
> kumar1 at ti.com; trini at konsulko.com; seanga2 at gmail.com;
> caleb.connolly at linaro.org; sjg at chromium.org; william.zhang at broadcom.com;
> stefan_b at posteo.net; quentin.schulz at cherry.de; tudor.ambarus at linaro.org;
> Takahiro.Kuwano at infineon.com; git (AMD-Xilinx) <git at amd.com>; Ashok Reddy
> Soma <ashok.reddy.soma at amd.com>
> Subject: Re: [PATCH] mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx
> flashes
> 
> On 09:12, Abbarapu, Venkatesh wrote:
> Hi Venkatesh,
> 
> > Hi Prasanth,
> >
> > > -----Original Message-----
> > > From: Prasanth Mantena <p-mantena at ti.com>
> > > Sent: Monday, November 25, 2024 2:19 PM
> > > To: Abbarapu, Venkatesh <venkatesh.abbarapu at amd.com>
> > > Cc: u-boot at lists.denx.de; j-humphreys at ti.com; Simek, Michal
> > > <michal.simek at amd.com>; jagan at amarulasolutions.com; vigneshr at ti.com;
> > > u- kumar1 at ti.com; trini at konsulko.com; seanga2 at gmail.com;
> > > caleb.connolly at linaro.org; sjg at chromium.org;
> > > william.zhang at broadcom.com; stefan_b at posteo.net;
> > > quentin.schulz at cherry.de; tudor.ambarus at linaro.org;
> > > Takahiro.Kuwano at infineon.com; git (AMD-Xilinx) <git at amd.com>; Ashok
> > > Reddy Soma <ashok.reddy.soma at amd.com>
> > > Subject: Re: [PATCH] mtd: spi-nor: Enable mt35xu512aba_fixups for
> > > all mt35xx flashes
> > >
> > > On 14:56, Venkatesh Yadav Abbarapu wrote:
> > > Hi Venkatesh,
> > > > Enable mt35xu512aba_fixups for all mt35 series flashes to work in
> > > > DTR mode, and return after nor->fixups is updated, otherwise it
> > > > will get overwritten with macronix_octal_fixups.
> > > > This flash works in DTR mode only if CONFIG_SPI_FLASH_MT35XU is
> > > > enabled and SPI_NOR_OCTAL_DTR_READ flag is set in id table.
> > > >
> > > > Additionally, a new flag, "SPI_XFER_SET_DDR", has been introduced
> > > > to instruct the OSPI controller driver to switch to DDR mode.
> > > >
> > > > Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma at amd.com>
> > > > Signed-off-by: Venkatesh Yadav Abbarapu
> > > > <venkatesh.abbarapu at amd.com>
> > > > ---
> > > >  drivers/mtd/spi/spi-nor-core.c | 8 +++++++-
> > > >  include/spi.h                  | 1 +
> > > >  2 files changed, 8 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/mtd/spi/spi-nor-core.c
> > > > b/drivers/mtd/spi/spi-nor-core.c index ec841fb13b..8d201433d5
> > > > 100644
> > > > --- a/drivers/mtd/spi/spi-nor-core.c
> > > > +++ b/drivers/mtd/spi/spi-nor-core.c
> > > > @@ -4073,6 +4073,7 @@ static int
> > > > spi_nor_micron_octal_dtr_enable(struct
> > > spi_nor *nor)
> > > >  	if (ret)
> > > >  		return ret;
> > > >
> > > > +	nor->spi->flags |= SPI_XFER_SET_DDR;
> > > >  	buf = SPINOR_MT_OCT_DTR;
> > > >  	op = (struct spi_mem_op)
> > > >
> > > 	SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
> @@ -4404,8
> > > > +4405,13 @@ void spi_nor_set_fixups(struct spi_nor *nor)  #endif
> > > >
> > > >  #ifdef CONFIG_SPI_FLASH_MT35XU
> > > > -	if (!strcmp(nor->info->name, "mt35xu512aba"))
> > > > +	if (!strcmp(nor->info->name, "mt35xu512aba") ||
> > > > +	    !strcmp(nor->info->name, "mt35xl512aba") ||
> > > > +	    !strcmp(nor->info->name, "mt35xu01g") ||
> > > > +	    !strcmp(nor->info->name, "mt35xu02g")) {
> > > >  		nor->fixups = &mt35xu512aba_fixups;
> > > > +		return;
> > > > +	}
> > > >  #endif
> > > >
> > > >  #if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> > > > diff --git a/include/spi.h b/include/spi.h index
> > > > 6944773b59..d7fef36662 100644
> > > > --- a/include/spi.h
> > > > +++ b/include/spi.h
> > > > @@ -164,6 +164,7 @@ struct spi_slave {
> > > >  #define SPI_XFER_U_PAGE		BIT(4)
> > > >  #define SPI_XFER_STACKED	BIT(5)
> > > >  #define SPI_XFER_LOWER		BIT(6)
> > > > +#define SPI_XFER_SET_DDR	BIT(7)
> > >
> > > Are we using this anywhere in the Controller driver ? What is the
> > > significance of this flag, when we can send the DDR info through the ops.
> > Yes...we will be checking this
> > If (spi->flags & SPI_XFER_SET_DDR) && op->cmd.dtr) then
> > 	setup the DDR mode in controller driver.
> 
> Is this change going to be for every read/write exec op or in some init function.
> Current driver has this setup dtr mode on checking the opcode.
> Curious to know, what does this extra flag bring something new to the driver.
> 
> Prasanth
I relooked the code and I see this flag is not required anymore. Will update the patch and send next version.

Thanks
Venkatesh
> 
> >
> > I need to send the controller change series.
> >
> > Thanks
> > Venkatesh
> > >
> > > >
> > > >  	/*
> > > >  	 * Flag indicating that the spi-controller has multi chip select
> > > > --
> > > > 2.25.1
> > > >
> > > >