[PATCH] arm64: zynqmp: Configure SoC RTC on SOM

Michal Simek michal.simek at amd.com
Wed Oct 23 08:09:23 CEST 2024


Use RTC available in HW on Kria SOM without using emulation that's why
configure it properly and disable emulated one.
Power on reset value of RTC Calibration register without battery backup is
not matching with crystal frequency which leads to RTC time drift. That's
why write CALIB_WRITE register with crystal frequency (0x7FFF). There is
also an option to write zero so that Linux will set default value (0x7FFF)
in driver probe but calibration 0 is not permited by DT schema.

Co-developed-by: Srinivas Goud <srinivas.goud at amd.com>
Signed-off-by: Srinivas Goud <srinivas.goud at amd.com>
Signed-off-by: Michal Simek <michal.simek at amd.com>
---

 arch/arm/dts/zynqmp-sm-k26-revA.dts  | 1 +
 configs/xilinx_zynqmp_kria_defconfig | 1 -
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 8056f6b176ed..8c43ade94053 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -387,6 +387,7 @@
 
 &rtc {
 	status = "okay";
+	calibration = <0x7fff>;
 };
 
 &lpd_dma_chan1 {
diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig
index dd4df0b2da17..0dddf69c5d05 100644
--- a/configs/xilinx_zynqmp_kria_defconfig
+++ b/configs/xilinx_zynqmp_kria_defconfig
@@ -187,7 +187,6 @@ CONFIG_DM_PWM=y
 CONFIG_PWM_CADENCE_TTC=y
 CONFIG_RESET_ZYNQMP=y
 CONFIG_DM_RTC=y
-CONFIG_RTC_EMULATION=y
 CONFIG_RTC_ZYNQMP=y
 CONFIG_SCSI=y
 CONFIG_ARM_DCC=y
-- 
2.43.0



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