[PATCH 2/4] imx: imxrt1050-evk: Fix missing clocks for mmc

[Fabio Estevam]

Hi Jesse,

On Thu, Oct 24, 2024 at 11:02 PM Jesse Taube <mr.bossman075 at gmail.com> wrote:
>
> Two of the clocks required by the usdhc1 controller are missing from the
> clock controller node. A recent change enables all the clocks in the
> esdhc node, which fails as they are not defined in the clock controller.
>
> Fixes: 76332fae769 ("mmc: fsl_esdhc_imx: Enable AHB/IPG clk with clk bulk API")
> Signed-off-by: Jesse Taube <Mr.Bossman075 at gmail.com>
> Cc: Peng Fan <peng.fan at nxp.com>
> ---
>  arch/arm/dts/imxrt1050.dtsi     | 2 +-
>  drivers/clk/imx/clk-imxrt1050.c | 3 +++
>  2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
> index 03e6a858a7b..a25eae9bd38 100644
> --- a/arch/arm/dts/imxrt1050.dtsi
> +++ b/arch/arm/dts/imxrt1050.dtsi
> @@ -87,7 +87,7 @@
>                         reg = <0x402c0000 0x4000>;
>                         interrupts = <110>;
>                         clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
> -                               <&clks IMXRT1050_CLK_OSC>,
> +                               <&clks IMXRT1050_CLK_AHB_PODF>,

I applied the whole series, but please consider fixing the kernel
devicetree and converting it to OF_UPSTREAM.

Thanks


>                                 <&clks IMXRT1050_CLK_USDHC1>;
>                         clock-names = "ipg", "ahb", "per";
>                         bus-width = <4>;
> diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
> index 788e0650a92..2c029ec5a6e 100644
> --- a/drivers/clk/imx/clk-imxrt1050.c
> +++ b/drivers/clk/imx/clk-imxrt1050.c
> @@ -144,6 +144,9 @@ static int imxrt1050_clk_probe(struct udevice *dev)
>         clk_dm(IMXRT1050_CLK_AHB_PODF,
>                imx_clk_divider("ahb_podf", "periph_sel",
>                                base + 0x14, 10, 3));
> +       clk_dm(IMXRT1050_CLK_IPG_PDOF,
> +              imx_clk_divider("ipg_podf", "ahb_podf",
> +                              base + 0x14, 8, 2));
>         clk_dm(IMXRT1050_CLK_USDHC1_PODF,
>                imx_clk_divider("usdhc1_podf", "usdhc1_sel",
>                                base + 0x24, 11, 3));
> --
> 2.45.2
>