[PATCH v1 00/20] SoCFPGA: Add Boot Support for Agilex 5 in U-Boot
tien.fong.chee at intel.com
tien.fong.chee at intel.com
Fri Sep 20 09:02:22 CEST 2024
From: Tien Fong Chee <tien.fong.chee at intel.com>
This patch set introduces boot support for the Altera SoCFPGA Agilex 5
platform in U-Boot. The changes include:
1. Board-specific configurations and setup required to enable Agilex 5
operation in U-Boot.
2. Integration of cache coherency unit (CCU) initialization routine,
including CCU conguration in DT.
3. Clock, firewall (configured in DT), SMMU, low level initialization
specific to Agilex 5.
4. Integration of memory initialization routine, including DDR setup.
This patch set has been tested on Agilex 5 devkit with QSPI boot (UBI/UBIFS)
and RAM boot (TFTP & ARM DS debugger).
Alif Zakuan Yuslaimi (1):
configs: socfpga: soc64: agilex5: Enable QSPI boot with UBI / UBIFS
Tien Fong Chee (18):
arm: socfpga: agilex5: Add new system manager base addresses
arm: socfpga: Add support for agilex5 clock manager
linker: Add SPL linker script for SoC64 devices
arm: socfpga: agilex5: Add low level initialization
arm: socfpga: Add handoff data support for SoCFPGA Agilex5 device
arm: dts: agilex5: Add HPS cache coherency unit configuration settings
arm: dts: agilex5: Add firewall configure settings
arm: dts: agilex5: Enable XGMAC
sysreset: Add reset support to SoCFPGA Agilex5 device
arm: socfpga: agilex5: Enable cache flush for system memory cache in
CCU
arm: socfpga: agilex5: Add SMMU initialization
arm: socfpga: agilex5: Update CPU info
arm: socfpga: Export board ID as U-Boot environment variable
configs: agilex5: Add configuration for malloc pool
arm: socfpga: smc: Add memory coherency support to mailbox command
arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGA
configs: socfpga: soc64: agilex5: Enable XGMAC
arm: socfpga: soc64: Add support for board_boot_order()
Tingting Meng (1):
ddr: altera: Add DDR driver for Agilex5 series
MAINTAINERS | 2 +
arch/arm/Kconfig | 1 +
arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 660 ++++++++++++++++++
arch/arm/dts/socfpga_agilex5.dtsi | 7 +
.../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 33 +
arch/arm/mach-socfpga/Makefile | 6 +
arch/arm/mach-socfpga/ccu_ncore3.c | 64 ++
arch/arm/mach-socfpga/include/mach/firewall.h | 23 +-
.../mach-socfpga/include/mach/handoff_soc64.h | 4 +-
arch/arm/mach-socfpga/include/mach/misc.h | 1 +
.../include/mach/reset_manager_soc64.h | 12 +-
.../include/mach/system_manager_soc64.h | 129 ++--
arch/arm/mach-socfpga/lowlevel_init_agilex5.S | 57 ++
arch/arm/mach-socfpga/misc.c | 24 +-
arch/arm/mach-socfpga/misc_soc64.c | 12 +-
arch/arm/mach-socfpga/smc_api.c | 13 +-
arch/arm/mach-socfpga/spl_agilex5.c | 84 +++
arch/arm/mach-socfpga/spl_soc64.c | 120 +++-
arch/arm/mach-socfpga/u-boot-spl-soc64.lds | 80 +++
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 10 +-
configs/socfpga_agilex5_defconfig | 6 +
drivers/ddr/altera/Makefile | 1 +
drivers/ddr/altera/iossm_mailbox.c | 613 ++++++++++++++++
drivers/ddr/altera/iossm_mailbox.h | 186 +++++
drivers/ddr/altera/sdram_agilex5.c | 377 ++++++++++
drivers/ddr/altera/sdram_soc64.c | 78 ++-
drivers/ddr/altera/sdram_soc64.h | 32 +-
drivers/sysreset/Kconfig | 7 +
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_socfpga_agilex5.c | 47 ++
include/configs/socfpga_soc64_common.h | 5 +
31 files changed, 2605 insertions(+), 90 deletions(-)
create mode 100644 arch/arm/mach-socfpga/ccu_ncore3.c
create mode 100644 arch/arm/mach-socfpga/lowlevel_init_agilex5.S
create mode 100644 arch/arm/mach-socfpga/spl_agilex5.c
create mode 100644 arch/arm/mach-socfpga/u-boot-spl-soc64.lds
create mode 100644 drivers/ddr/altera/iossm_mailbox.c
create mode 100644 drivers/ddr/altera/iossm_mailbox.h
create mode 100644 drivers/ddr/altera/sdram_agilex5.c
create mode 100644 drivers/sysreset/sysreset_socfpga_agilex5.c
--
2.25.1
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