[PATCH v1 09/20] sysreset: Add reset support to SoCFPGA Agilex5 device

[tien.fong.chee at intel.com]

From: Tien Fong Chee <tien.fong.chee at intel.com>

The reset driver can support both cold reset and warm reset with SMCC
to ATF.

Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
---
 arch/arm/Kconfig                            |  1 +
 drivers/sysreset/Kconfig                    |  7 +++
 drivers/sysreset/Makefile                   |  1 +
 drivers/sysreset/sysreset_socfpga_agilex5.c | 47 +++++++++++++++++++++
 4 files changed, 56 insertions(+)
 create mode 100644 drivers/sysreset/sysreset_socfpga_agilex5.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ba0359fed5a..8e9a39e7d23 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1123,6 +1123,7 @@ config ARCH_SOCFPGA
 	select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
 	  TARGET_SOCFPGA_SOC64
+	select SYSRESET_SOCFPGA_AGILEX5 if TARGET_SOCFPGA_AGILEX5
 	imply CMD_DM
 	imply CMD_MTDPARTS
 	imply CRC32_VERIFY
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 121194e4418..8dc1e7fec58 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -156,6 +156,13 @@ config SYSRESET_SOCFPGA_SOC64
 	  This enables the system reset driver support for Intel SOCFPGA
 	  SoC64 SoCs.
 
+config SYSRESET_SOCFPGA_AGILEX5
+	bool "Enable support for Intel SOCFPGA AGILEX5 device"
+	depends on ARCH_SOCFPGA && TARGET_SOCFPGA_AGILEX5
+	help
+	  This enables the system reset driver support for Intel SOCFPGA
+	  AGILEX5 device.
+
 config SYSRESET_TEGRA
 	bool "Tegra PMC system reset driver"
 	depends on ARCH_TEGRA
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index a6a0584585c..c090db48af4 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
 obj-$(CONFIG_SYSRESET_SBI) += sysreset_sbi.o
 obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
 obj-$(CONFIG_SYSRESET_SOCFPGA_SOC64) += sysreset_socfpga_soc64.o
+obj-$(CONFIG_SYSRESET_SOCFPGA_AGILEX5) += sysreset_socfpga_agilex5.o
 obj-$(CONFIG_SYSRESET_TEGRA) += sysreset_tegra.o
 obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
 obj-$(CONFIG_$(SPL_TPL_)SYSRESET_TPS65910) += sysreset_tps65910.o
diff --git a/drivers/sysreset/sysreset_socfpga_agilex5.c b/drivers/sysreset/sysreset_socfpga_agilex5.c
new file mode 100644
index 00000000000..3cb7849ec88
--- /dev/null
+++ b/drivers/sysreset/sysreset_socfpga_agilex5.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <cpu_func.h>
+#include <dm.h>
+#include <env.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/system.h>
+
+static int socfpga_sysreset_request(struct udevice *dev,
+				    enum sysreset_t type)
+{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+	const char *reset = env_get("reset");
+
+	if (reset && !strcmp(reset, "warm")) {
+		/* Ensure content in dcache is flushed to system memory */
+		flush_dcache_all();
+
+		/* request a warm reset */
+		puts("Do warm reset now...\n");
+
+		/* doing architecture system reset */
+		psci_system_reset2(0, 0);
+	} else {
+		puts("Issuing cold reset REBOOT_HPS\n");
+		psci_system_reset();
+	}
+#endif
+
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops socfpga_sysreset = {
+	.request = socfpga_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_socfpga) = {
+	.id	= UCLASS_SYSRESET,
+	.name	= "socfpga_sysreset",
+	.ops	= &socfpga_sysreset,
+};
-- 
2.25.1