[PATCH v3 20/33] README: Drop SoC-specific comment about SPL

[Simon Glass]

This should not be in the generic README file, so drop it.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

Changes in v3:
- Move to earlier in the series

 README | 10 +---------
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/README b/README
index c7ee06a21dd..78d91a2f62d 100644
--- a/README
+++ b/README
@@ -213,15 +213,7 @@ board_init_r():
 		there.
 
 	SPL-specific notes:
-	- stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and
-		CONFIG_SYS_FSL_HAS_CCI400
-
-		Defined For SoC that has cache coherent interconnect
-		CCN-400
-
-		CONFIG_SYS_FSL_HAS_CCN504
-
-		Defined for SoC that has cache coherent interconnect CCN-504
+	- stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined
 
 The following options need to be configured:
 
-- 
2.34.1