[PATCH v2 07/11] sunxi: Add support for UART1 on PG pins for the V3/S3

[Paul Kocialkowski]

From: Paul Kocialkowski <contact at paulk.fr>

The V3/S3 has extra pins for UART1 on PG pins, which are not present
on the V3s. Add support for them and make them the default UART1 pins
on the V3. Note that PE pins are also available for UART1 but almost
never used since they also provide the CSI I2C lines.

Signed-off-by: Paul Kocialkowski <contact at paulk.fr>
---
 arch/arm/mach-sunxi/board.c | 4 ++++
 include/sunxi_gpio.h        | 1 +
 2 files changed, 5 insertions(+)

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index a1a02b0fae50..d1b27b062d6d 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -169,6 +169,10 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
 	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I_V3)
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_V3_GPG_UART1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_V3_GPG_UART1);
+	sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3)
 	sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2);
 	sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2);
diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h
index e166b9758f44..7d142f65ea8a 100644
--- a/include/sunxi_gpio.h
+++ b/include/sunxi_gpio.h
@@ -141,6 +141,7 @@ enum sunxi_gpio_number {
 #define SUN8I_GPG_SDC1		2
 #define SUN8I_GPG_UART1		2
 #define SUN5I_GPG_UART1		4
+#define SUN8I_V3_GPG_UART1	2
 
 #define SUN6I_GPH_PWM		2
 #define SUN8I_GPH_PWM		2
-- 
2.49.0