[PATCH v1 0/3] socfpga: Agilex5: Fix dcache usage in SPL and SMC mailbox flow

[Boon Khai Ng]

Hi all,

Proposing the following fix to address data cache handling issues and missing
weak functions in the Agilex5 platform, particularly in the SPL build and SMC
mailbox communication path. It ensures correctness in cache operations,
resolves undefined symbol errors, and provides the necessary configuration
to disable data cache in SPL where required.

Patch Summary:
[1/3] arch: arm: mach-socfpga: smc: Add dcache flushing and invalidation
in smc_send_mailbox()

Ensures that the response buffer from the secure monitor call (SMC) is
properly invalidated in cache to avoid stale data access.

Updates pointer arithmetic by replacing u64 with uintptr_t to improve
portability and correctness.

[2/3] arch: arm: lib: cache_v8: agilex5: Add weak function in cache_v8

Adds weak implementations for dcache_disable, dcache_status, and
mmu_status to prevent undefined symbol errors during SPL
build when data cache is not enabled.

These stubs are used by other SPL components like  QSPI driver logic.

[3/3] configs: agilex5: Enable config SPL_SYS_DCACHE_OFF

Disables SPL data cache explicitly via CONFIG_SPL_SYS_DCACHE_OFF
to align with the above changes and prevent inconsistencies during early boot.

This patchset has been tested on Agilex5 and resolves the SPL build
issues related to missing symbols, while also improving runtime
robustness in SMC-based communication.

Let me know if there are any concerns or feedback. Thank you!

Boon Khai Ng (3):
  arch: arm: mach-socfpga: smc: Add dcache flushing and invalidation in
    smc_send_mailbox()
  arch: arm: lib: cache_v8: agilex5: Add weak function in cache_v8
  configs: agilex5: Enable config SPL_SYS_DCACHE_OFF

 arch/arm/lib/cache.c              | 17 +++++++++++++++++
 arch/arm/mach-socfpga/smc_api.c   |  1 +
 configs/socfpga_agilex5_defconfig |  1 +
 3 files changed, 19 insertions(+)

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2.35.3