[PATCH 02/10] mmc: rockchip: fix clock get wrong index

[Jonas Karlman]

Hi,

On 8/7/2025 9:44 AM, WeiHao Li wrote:
> Signed-off-by: WeiHao Li <ieiao at outlook.com>
> ---
>  drivers/mmc/rockchip_dw_mmc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
> index 7a72abaa38..a3f001d7e7 100644
> --- a/drivers/mmc/rockchip_dw_mmc.c
> +++ b/drivers/mmc/rockchip_dw_mmc.c
> @@ -132,7 +132,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
>  
>  	ret = clk_get_by_phandle(dev, &dtplat->clocks[1], &priv->clk);
>  #else
> -	ret = clk_get_by_index(dev, 1, &priv->clk);
> +	ret = clk_get_by_index(dev, 0, &priv->clk);

Index 1 is the ciu clk and matches the linux driver and u-boot driver
usage of the clock.

Please explain why you think this should use index 0?

Could it be the device tree that is using "wrong" clock order?,
the dt-binding define following order: biu, ciu, ciu-drive, ciu-sample.

Or possible an issue in the rk3368 u-boot clk driver?

Also if this is wrong then &dtplat->clocks[1] should also be changed.

Regards,
Jonas

>  #endif
>  	if (ret < 0 && ret != -ENOSYS)
>  		return log_msg_ret("clk", ret);