[PATCH v2 3/3] configs: agilex5: Enable config SPL_SYS_DCACHE_OFF

[Chee, Tien Fong]

> -----Original Message-----
> From: Ng, Boon Khai <boon.khai.ng at altera.com>
> Sent: Thursday, August 14, 2025 11:18 AM
> To: U-boot Openlist <u-boot at lists.denx.de>
> Cc: Tom Rini <trini at konsulko.com>; Simon Glass <sjg at chromium.org>;
> Marek Vasut <marex at denx.de>; Simon Goldschmidt
> <simon.k.r.goldschmidt at gmail.com>; Chee, Tien Fong
> <tien.fong.chee at altera.com>; Maniyam, Dinesh
> <dinesh.maniyam at altera.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi at altera.com>; Lim, Jit Loon <jit.loon.lim at altera.com>;
> Ng, Boon Khai <boon.khai.ng at altera.com>; Kathpalia, Tanmay
> <tanmay.kathpalia at altera.com>; Ilias Apalodimas
> <ilias.apalodimas at linaro.org>; Jerome Forissier
> <jerome.forissier at linaro.org>; Rao, Mahesh <mahesh.rao at altera.com>
> Subject: [PATCH v2 3/3] configs: agilex5: Enable config SPL_SYS_DCACHE_OFF
> 
> Add SPL_SYS_DCACHE_OFF to Agilex5 defconfig to disable data cache for SPL
> 
> Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia at altera.com>
> Signed-off-by: Boon Khai Ng <boon.khai.ng at altera.com>
> ---
>  configs/socfpga_agilex5_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/configs/socfpga_agilex5_defconfig
> b/configs/socfpga_agilex5_defconfig
> index 33a6221979a..8c31dcfea11 100644
> --- a/configs/socfpga_agilex5_defconfig
> +++ b/configs/socfpga_agilex5_defconfig
> @@ -45,6 +45,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
>  CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xbfa00000
>  CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
>  CONFIG_SPL_CACHE=y
> +CONFIG_SPL_SYS_DCACHE_OFF=y
>  CONFIG_SPL_MTD=y
>  CONFIG_SPL_SPI_FLASH_MTD=y
>  CONFIG_SPL_SPI_LOAD=y
> --
> 2.35.3

Reviewed-by: Tien Fong Chee <tien.fong.chee at altera.com>

Best regards,
Tien Fong