[PATCH v2 3/3] drivers: fpga: Check bitstream address doesn't exceed 512MB

[Ravulapalli, Naresh Kumar]

Hi Tien Fong

On 25-Aug-25 3:12 PM, Chee, Tien Fong wrote:
> Hi Naresh,
> 
>> -----Original Message-----
>> From: Ravulapalli, Naresh Kumar <naresh.kumar.ravulapalli at altera.com>
>> Sent: Wednesday, August 20, 2025 3:32 PM
>> To: u-boot at lists.denx.de
>> Cc: Marek Vasut <marek.vasut at mailbox.org>; Simon Goldschmidt
>> <simon.k.r.goldschmidt at gmail.com>; Michal Simek
>> <michal.simek at amd.com>; Chee, Tien Fong <tien.fong.chee at altera.com>;
>> Ng, Boon Khai <boon.khai.ng at altera.com>; Yuslaimi, Alif Zakuan
>> <alif.zakuan.yuslaimi at altera.com>; Tom Rini <trini at konsulko.com>;
>> Ravulapalli, Naresh Kumar <naresh.kumar.ravulapalli at altera.com>
>> Subject: [PATCH v2 3/3] drivers: fpga: Check bitstream address doesn't
>> exceed 512MB
>>
>> Secure Device Manager(SDM) has only 512MB window address space to HPS
>> over PSI BE link. The default access range is 0x0 to 0x1FFFFFFF.
>> To allow SDM accessing the address space more than 512MB, SMMU has to
>> be setup for address translation.
>>
>> A conditional check is added to not allow the fpga reconfiguration for any
>> bitstream data where address exceeds 512MB, unless PSI BE link address
>> translation is setup in SMMU.
>>
>> Signed-off-by: Naresh Kumar Ravulapalli
>> <nareshkumar.ravulapalli at altera.com>
>> ---
>>   arch/arm/mach-socfpga/include/mach/smmu_s10.h |  6 ++++++
>>   drivers/fpga/intel_sdm_mb.c                   | 13 +++++++++++++
>>   2 files changed, 19 insertions(+)
>>
>> diff --git a/arch/arm/mach-socfpga/include/mach/smmu_s10.h
>> b/arch/arm/mach-socfpga/include/mach/smmu_s10.h
>> index 209caa86e38..d611664e227 100644
>> --- a/arch/arm/mach-socfpga/include/mach/smmu_s10.h
>> +++ b/arch/arm/mach-socfpga/include/mach/smmu_s10.h
>> @@ -30,6 +30,12 @@
>>
>>   #define SMMU_SID_SDM2HPS_PSI_BE		0
>>
>> +#define SDM2HPS_PSI_BE_ADDR_BASE	0
>> +/* PSI BE 512MB address window */
>> +#define SDM2HPS_PSI_BE_WINDOW_SZ	0x20000000
>> +#define SDM2HPS_PSI_BE_ADDR_END		\
>> +	(SDM2HPS_PSI_BE_ADDR_BASE + SDM2HPS_PSI_BE_WINDOW_SZ -
>> 1)
>> +
>>   void socfpga_init_smmu(void);
>>   int is_smmu_bypass(void);
>>   int is_smmu_stream_id_enabled(u32 stream_id); diff --git
>> a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c index
>> 5f4aae47d6d..1bbb717015b 100644
>> --- a/drivers/fpga/intel_sdm_mb.c
>> +++ b/drivers/fpga/intel_sdm_mb.c
>> @@ -10,6 +10,7 @@
>>   #include <watchdog.h>
>>   #include <asm/arch/mailbox_s10.h>
>>   #include <asm/arch/smc_api.h>
>> +#include <asm/arch/smmu_s10.h>
>>   #include <asm/cache.h>
>>   #include <cpu_func.h>
>>   #include <linux/delay.h>
>> @@ -1031,6 +1032,18 @@ int intel_sdm_mb_load(Altera_desc *desc, const
>> void *rbf_data, size_t rbf_size)
>>
>>   	flush_dcache_range((unsigned long)rbf_data, (unsigned
>> long)(rbf_data + rbf_size));
>>
>> +	/*
>> +	 * Don't start the FPGA reconfiguration if bitstream location exceed
>> the
>> +	 * PSI BE 512MB address window and SMMU is not setup for PSI BE
>> address
>> +	 * translation.
>> +	 */
>> +	if (((u64)rbf_data + rbf_size) >= SDM2HPS_PSI_BE_ADDR_END &&
>> +	    !is_smmu_stream_id_enabled(SMMU_SID_SDM2HPS_PSI_BE)) {
>> +		printf("Failed: Bitstream location must not exceed 0x%08x\n",
>> +		       SDM2HPS_PSI_BE_ADDR_END);
>> +		return -EINVAL;
>> +	}
> 
> This function is common for all SoC64 devices, but above limitation is not applicable to Agilex5

intel_sdm_mb_load() is defined twice within a #ifdef condition. 512 MB 
limitation is only addressed in the second function definition. Could 
you please confirm if this is not the intended implementation?

> 
>> +
>>   	debug("Sending MBOX_RECONFIG...\n");
>>   	ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG,
>> MBOX_CMD_DIRECT, 0,
>>   			    NULL, 0, &resp_len, resp_buf);
>> --
>> 2.35.3
> 

Kind Regards
Naresh