[PATCH v2 4/4] arch: arm: socfpga: Configure USB3 System Manager registers

[Chee, Tien Fong]

> -----Original Message-----
> From: Ravulapalli, Naresh Kumar <naresh.kumar.ravulapalli at altera.com>
> Sent: Thursday, August 28, 2025 2:24 PM
> To: u-boot at lists.denx.de
> Cc: Marek Vasut <marek.vasut at mailbox.org>; Simon Goldschmidt
> <simon.k.r.goldschmidt at gmail.com>; Chee, Tien Fong
> <tien.fong.chee at altera.com>; Tom Rini <trini at konsulko.com>; Ravulapalli,
> Naresh Kumar <naresh.kumar.ravulapalli at altera.com>
> Subject: [PATCH v2 4/4] arch: arm: socfpga: Configure USB3 System Manager
> registers
> 
> For successful reset staggering pulse operation, reset pulse override bit is set.
> Port overcurrent bit 1, which in reality reflects PIPE power present signal is
> set to avoid giving false information of Vbus status to HPS controller.
> 
> Signed-off-by: Naresh Kumar Ravulapalli
> <nareshkumar.ravulapalli at altera.com>
> ---
>  .../include/mach/system_manager_soc64.h       | 12 +++++++++
>  arch/arm/mach-socfpga/system_manager_soc64.c  | 26
> ++++++++++++++++++-
>  2 files changed, 37 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> index c2ca0a50e35..c0392d99863 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
> @@ -33,6 +33,7 @@ void populate_sysmgr_pinmux(void);
>  #define SYSMGR_SOC64_ECC_INTMASK_CLR		0x98
>  #define SYSMGR_SOC64_ECC_INTMASK_SERR		0x9C
>  #define SYSMGR_SOC64_ECC_INTMASK_DERR		0xA0
> +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0	0x1F0
>  #define SYSMGR_SOC64_MPFE_CONFIG		0x228
>  #define SYSMGR_SOC64_BOOT_SCRATCH_POR0		0x258
>  #define SYSMGR_SOC64_BOOT_SCRATCH_POR1		0x25C
> @@ -47,6 +48,17 @@ void populate_sysmgr_pinmux(void);
>  #define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK
> 	BIT(0)
>  #define
> ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_
> MASK	BIT(0)
>  #define
> ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK	BIT(1)
> +
> +/*
> + * Bits for SYSMGR_SOC64_USB3_MISC_CTRL_REG0
> + * Bits[14:13] Port Overcurrent
> + * Bit[12] Reset Pulse Override
> + */
> +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR
> 	GENMASK(14, 13)
> +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR	BIT(12)
> +#define SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR	1
> +/* BIT 1 actually reflects PIPE power present signal */
> +#define SET_USB3_MISC_CTRL_REG0_PORT_OVR_CURR_BIT_1	2
>  #else
>  #define SYSMGR_SOC64_NAND_AXUSER		0x5c
>  #define SYSMGR_SOC64_DMA_L3MASTER		0x74
> diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c
> b/arch/arm/mach-socfpga/system_manager_soc64.c
> index 4b42158be9d..88d538cdcda 100644
> --- a/arch/arm/mach-socfpga/system_manager_soc64.c
> +++ b/arch/arm/mach-socfpga/system_manager_soc64.c
> @@ -1,16 +1,36 @@
>  // SPDX-License-Identifier: GPL-2.0
>  /*
>   * Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
> - *
> + * Copyright (C) 2025 Altera Corporation <www.altera.com>
>   */
> 
>  #include <asm/arch/handoff_soc64.h>
>  #include <asm/arch/system_manager.h>
>  #include <asm/global_data.h>
>  #include <asm/io.h>
> +#include <linux/bitfield.h>
> 
>  DECLARE_GLOBAL_DATA_PTR;
> 
> +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
> +/*
> + * Setting RESET_PULSE_OVERRIDE bit for successful reset staggering
> +pulse
> + * generation and setting PORT_OVERCURRENT bit so that until we turn on
> +the
> + * Vbus, it doesn't give false information about Vbus to the HPS controller.
> + */
> +static void sysmgr_config_usb3(void)
> +{
> +	u32 reg_val = 0;
> +
> +	reg_val = readl(socfpga_get_sysmgr_addr() +
> SYSMGR_SOC64_USB3_MISC_CTRL_REG0);
> +	reg_val |=
> FIELD_PREP(SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR,
> +
> 	SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR);
> +	reg_val |=
> FIELD_PREP(SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR,
> +
> 	SET_USB3_MISC_CTRL_REG0_PORT_OVR_CURR_BIT_1);
> +	writel(reg_val, socfpga_get_sysmgr_addr() +
> +SYSMGR_SOC64_USB3_MISC_CTRL_REG0);
> +}
> +#endif
> +
>  /*
>   * Configure all the pin muxes
>   */
> @@ -18,6 +38,10 @@ void sysmgr_pinmux_init(void)  {
>  	populate_sysmgr_pinmux();
>  	populate_sysmgr_fpgaintf_module();
> +
> +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
> +	sysmgr_config_usb3();
> +#endif
>  }
> 
>  /*
> --
> 2.35.3

Reviewed-by: Tien Fong Chee <tien.fong.chee at altera.com>

Best regards,
Tien Fong