[PATCH v3 2/3] phy: rockchip: naneng-combphy: Add support for RK3576
Kever Yang
kever.yang at rock-chips.com
Sat Aug 30 16:57:26 CEST 2025
On 2025/8/2 04:43, Jonas Karlman wrote:
> From: Jon Lin <jon.lin at rock-chips.com>
>
> Add support for the PCIe/USB3/SATA combo PHYs used in the RK3576 SoC.
>
> Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
>
> Signed-off-by: Jon Lin <jon.lin at rock-chips.com>
> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>
Thanks,
- Kever
> ---
> v3: Ensure USB3OTG U3 port is enabled when USB3 PHY is used
> v2: New patch
>
> I have only verified that the PCIe and USB3 mode config works.
> ---
> .../rockchip/phy-rockchip-naneng-combphy.c | 147 ++++++++++++++++++
> 1 file changed, 147 insertions(+)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> index 7f107a11606b..8c116882ecfb 100644
> --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -388,6 +388,149 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
> .combphy_cfg = rk3568_combphy_cfg,
> };
>
> +static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
> +{
> + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
> + u32 val;
> +
> + switch (priv->mode) {
> + case PHY_TYPE_PCIE:
> + param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
> + param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
> + param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
> + param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
> + break;
> + case PHY_TYPE_USB3:
> + /* Set SSC downward spread spectrum */
> + val = readl(priv->mmio + (0x1f << 2));
> + val &= ~GENMASK(5, 4);
> + val |= 0x01 << 4;
> + writel(val, priv->mmio + 0x7c);
> +
> + /* Enable adaptive CTLE for USB3.0 Rx */
> + val = readl(priv->mmio + (0x0e << 2));
> + val &= ~GENMASK(0, 0);
> + val |= 0x01;
> + writel(val, priv->mmio + (0x0e << 2));
> +
> + /* Set PLL KVCO fine tuning signals */
> + val = readl(priv->mmio + (0x20 << 2));
> + val &= ~(0x7 << 2);
> + val |= 0x2 << 2;
> + writel(val, priv->mmio + (0x20 << 2));
> +
> + /* Set PLL LPF R1 to su_trim[10:7]=1001 */
> + writel(0x4, priv->mmio + (0xb << 2));
> +
> + /* Set PLL input clock divider 1/2 */
> + val = readl(priv->mmio + (0x5 << 2));
> + val &= ~(0x3 << 6);
> + val |= 0x1 << 6;
> + writel(val, priv->mmio + (0x5 << 2));
> +
> + /* Set PLL loop divider */
> + writel(0x32, priv->mmio + (0x11 << 2));
> +
> + /* Set PLL KVCO to min and set PLL charge pump current to max */
> + writel(0xf0, priv->mmio + (0xa << 2));
> +
> + /* Set Rx squelch input filler bandwidth */
> + writel(0x0d, priv->mmio + (0x14 << 2));
> +
> + param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
> + param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
> + param_write(priv->phy_grf, &cfg->usb_mode_set, true);
> + param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true);
> + break;
> + case PHY_TYPE_SATA:
> + /* Enable adaptive CTLE for SATA Rx */
> + val = readl(priv->mmio + (0x0e << 2));
> + val &= ~GENMASK(0, 0);
> + val |= 0x01;
> + writel(val, priv->mmio + (0x0e << 2));
> + /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
> + writel(0x8F, priv->mmio + (0x06 << 2));
> +
> + param_write(priv->phy_grf, &cfg->con0_for_sata, true);
> + param_write(priv->phy_grf, &cfg->con1_for_sata, true);
> + param_write(priv->phy_grf, &cfg->con2_for_sata, true);
> + param_write(priv->phy_grf, &cfg->con3_for_sata, true);
> + param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
> + param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
> + break;
> + case PHY_TYPE_SGMII:
> + case PHY_TYPE_QSGMII:
> + default:
> + dev_err(priv->dev, "incompatible PHY type\n");
> + return -EINVAL;
> + }
> +
> + /* 100MHz refclock signal is good */
> + clk_set_rate(&priv->ref_clk, 100000000);
> + param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
> + if (priv->mode == PHY_TYPE_PCIE) {
> + /* gate_tx_pck_sel length select work for L1SS */
> + writel(0xc0, priv->mmio + 0x74);
> +
> + /* PLL KVCO tuning fine */
> + val = readl(priv->mmio + (0x20 << 2));
> + val &= ~(0x7 << 2);
> + val |= 0x2 << 2;
> + writel(val, priv->mmio + (0x20 << 2));
> +
> + /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
> + writel(0x4c, priv->mmio + (0x1b << 2));
> +
> + /* Set up su_trim: T3_P1 650mv */
> + writel(0x90, priv->mmio + (0xa << 2));
> + writel(0x43, priv->mmio + (0xb << 2));
> + writel(0x88, priv->mmio + (0xc << 2));
> + writel(0x56, priv->mmio + (0xd << 2));
> + }
> +
> + return 0;
> +}
> +
> +static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = {
> + /* pipe-phy-grf */
> + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
> + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
> + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
> + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
> + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
> + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
> + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
> + .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
> + .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
> + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
> + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
> + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
> + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
> + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
> + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
> + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
> + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
> + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
> + .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
> + .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
> + .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
> + .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
> + /* php-grf */
> + .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 },
> + .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 },
> + .u3otg1_port_en = { 0x0038, 15, 0, 0x0181, 0x1100 },
> +};
> +
> +static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = {
> + .num_phys = 2,
> + .phy_ids = {
> + 0x2b050000,
> + 0x2b060000,
> + },
> + .grfcfg = &rk3576_combphy_grfcfgs,
> + .combphy_cfg = rk3576_combphy_cfg,
> +};
> +
> static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
> {
> const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
> @@ -499,6 +642,10 @@ static const struct udevice_id rockchip_combphy_ids[] = {
> .compatible = "rockchip,rk3568-naneng-combphy",
> .data = (ulong)&rk3568_combphy_cfgs
> },
> + {
> + .compatible = "rockchip,rk3576-naneng-combphy",
> + .data = (ulong)&rk3576_combphy_cfgs
> + },
> {
> .compatible = "rockchip,rk3588-naneng-combphy",
> .data = (ulong)&rk3588_combphy_cfgs
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