[PATCH 5/8] rockchip: clk: clk_rk3528: Add dummy CLK_REF_PCIE_INNER_PHY support

[Kever Yang]

On 2025/7/31 07:52, Jonas Karlman wrote:
> Add dummy support for the CLK_REF_PCIE_INNER_PHY clock to allow probe of
> the phy-rockchip-naneng-combphy driver on RK3528.
>
> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/clk/rockchip/clk_rk3528.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c
> index 06f20895accf..d58557ff56de 100644
> --- a/drivers/clk/rockchip/clk_rk3528.c
> +++ b/drivers/clk/rockchip/clk_rk3528.c
> @@ -1535,6 +1535,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
>   	/* Might occur in cru assigned-clocks, can be ignored here */
>   	case ACLK_BUS_VOPGL_ROOT:
>   	case BCLK_EMMC:
> +	case CLK_REF_PCIE_INNER_PHY:
>   	case XIN_OSC0_DIV:
>   		ret = 0;
>   		break;