[PATCH v2 1/5] dt-bindings: mfd: rk806: Allow to customize PMIC reset mode

[Kever Yang]

On 2025/8/13 22:07, Quentin Schulz wrote:
> From: Quentin Schulz <quentin.schulz at cherry.de>
>
> The RK806 PMIC allows to configure its reset/restart behavior whenever
> the PMIC is reset either programmatically or via some external pins
> (e.g. PWRCTRL or RESETB).
>
> The following modes exist:
>   - 0; restart PMU,
>   - 1; reset all power off reset registers and force state to switch to
>     ACTIVE mode,
>   - 2; same as mode 1 and also pull RESETB pin down for 5ms,
>
> For example, some hardware may require a full restart (mode 0) in order
> to function properly as regulators are shortly interrupted in this mode.
>
> This is the case for RK3588 Jaguar and RK3588 Tiger which have a
> companion microcontroller running on an independent power supply and
> monitoring the PMIC power rail to know the state of the main system.
> When it detects a restart, it resets its own IPs exposed to the main
> system as if to simulate its own reset. Failing to perform this fake
> reset of the microcontroller may break things (e.g. watchdog not
> automatically disabled, buzzer still running until manually disabled,
> leftover configuration from previous main system state, etc...).
>
> Some other systems may be depending on the power rails to not be
> interrupted even for a small amount of time[1].
>
> This allows to specify how the PMIC should perform on the hardware level
> and may differ between hardware designs, so a DT property seems
> warranted. I unfortunately do not see how this could be made generic
> enough to make it a non-vendor property.
>
> [1] https://lore.kernel.org/linux-rockchip/2577051.irdbgypaU6@workhorse/
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> Signed-off-by: Quentin Schulz <quentin.schulz at cherry.de>
> Reviewed-by: "Rob Herring (Arm)" <robh at kernel.org>
> Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-1-ce05d041b45f@cherry.de
> Signed-off-by: Lee Jones <lee at kernel.org>
>
> [ upstream commit: 404005d1083997daec7236620b9ba14bccdce449 ]
>
> (cherry picked from commit 8ee72356e9844265334fd344bc05139d1f615c4d)
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
>   dts/upstream/Bindings/mfd/rockchip,rk806.yaml | 21 +++++++++++++++++++++
>   1 file changed, 21 insertions(+)
>
> diff --git a/dts/upstream/Bindings/mfd/rockchip,rk806.yaml b/dts/upstream/Bindings/mfd/rockchip,rk806.yaml
> index 3c2b06629b75ea94f90712470bf14ed7fc16d68d..eb5bca31948ef0d39c46025d0cca65b8b4105a50 100644
> --- a/dts/upstream/Bindings/mfd/rockchip,rk806.yaml
> +++ b/dts/upstream/Bindings/mfd/rockchip,rk806.yaml
> @@ -31,6 +31,27 @@ properties:
>   
>     system-power-controller: true
>   
> +  rockchip,reset-mode:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1, 2]
> +    description:
> +      Mode to use when a reset of the PMIC is triggered.
> +
> +      The reset can be triggered either programmatically, via one of
> +      the PWRCTRL pins (provided additional configuration) or
> +      asserting RESETB pin low.
> +
> +      The following modes are supported
> +
> +      - 0; restart PMU,
> +      - 1; reset all power off reset registers and force state to
> +        switch to ACTIVE mode,
> +      - 2; same as mode 1 and also pull RESETB pin down for 5ms,
> +
> +      For example, some hardware may require a full restart (mode 0)
> +      in order to function properly as regulators are shortly
> +      interrupted in this mode.
> +
>     vcc1-supply:
>       description:
>         The input supply for dcdc-reg1.
>