[PATCH 08/10] rockchip: rk3588: Disable USB3OTG U3 ports early

[Kever Yang]

On 2025/7/22 06:07, Jonas Karlman wrote:
> The RK3588 SoC comes with USB OTG support using a DWC3 controller with
> a USB2 PHY and a USB3 PHY (USBDP PHY).
>
> Some board designs may not use the USBDP PHY for USB3 purpose. For these
> board to use USB OTG the input clock source must change to use UTMI clk
> instead of PIPE clk.
>
> Change to always disable the USB3OTG U3 ports early and leave it to the
> USBDP PHY driver to re-enable the U3 port when a usb3-phy is described
> in the board device tree.
>
> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
>   arch/arm/mach-rockchip/rk3588/rk3588.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c
> index e2278ff792b4..c01a40020896 100644
> --- a/arch/arm/mach-rockchip/rk3588/rk3588.c
> +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
> @@ -15,6 +15,10 @@
>   #include <asm/arch-rockchip/hardware.h>
>   #include <asm/arch-rockchip/ioc_rk3588.h>
>   
> +#define USB_GRF_BASE			0xfd5ac000
> +#define USB3OTG0_CON1			0x001c
> +#define USB3OTG1_CON1			0x0034
> +
>   #define FIREWALL_DDR_BASE		0xfe030000
>   #define FW_DDR_MST5_REG			0x54
>   #define FW_DDR_MST13_REG		0x74
> @@ -184,6 +188,10 @@ int arch_cpu_init(void)
>   	/* Disable JTAG exposed on SDMMC */
>   	rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG);
>   #endif
> +
> +	/* Disable USB3OTG U3 ports, later enabled by USBDP PHY driver */
> +	writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
> +	writel(0xffff0188, USB_GRF_BASE + USB3OTG1_CON1);
>   #endif
>   
>   	return 0;