[PATCH 2/5] rockchip: Improve ARMv7 support for ROCKCHIP_COMMON_STACK_ADDR

[Jonas Karlman]

Hi Quentin,

On 2025-02-05 18:07, Quentin Schulz wrote:
> Hi Jonas,
> 
> On 1/27/25 12:48 AM, Jonas Karlman wrote:
>> A few Rockchip ARMv7 SoCs use 0x60000000 as DRAM base address instead of
> 
> Are there known exceptions? Among the list you provided I see RV1126 is 
> missing but is ARMv7-based. Is it an oversight or done on purpose? I 
> couldn't quickly find the TRM so no clue.

The default if tested SoCs below is the only 6 SoCs that seem to use the
0x60000000 base, both in mainline and vendor U-Boot. RV1126, RK3288 and
incoming RK3506 all use 0x0 as base address.

> 
>> the more common 0x0 DRAM base address used on AArch64 SoCs.
>>
>> Add default options that should work for these ARMv7 SoCs. Same offsets
>> as before are used, just below 64 MiB. Hex values have also been padded
>> to improve alignment.
>>
>> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
>> ---
>>   arch/arm/mach-rockchip/Kconfig | 35 +++++++++++++++++++++++-----------
>>   1 file changed, 24 insertions(+), 11 deletions(-)
>>
>> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
>> index 5aa9e0f1af3b..da20d3233fe3 100644
>> --- a/arch/arm/mach-rockchip/Kconfig
>> +++ b/arch/arm/mach-rockchip/Kconfig
>> @@ -637,40 +637,53 @@ source "arch/arm/mach-rockchip/rv1126/Kconfig"
>>   if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR
>>   
>>   config CUSTOM_SYS_INIT_SP_ADDR
>> -	default 0x3f00000
>> +	default 0x63f00000 if SPL_TEXT_BASE = 0x60000000
>> +	default 0x03f00000 if SPL_TEXT_BASE = 0x00000000
> 
> A bit sad we cannot do arithmetic here in Kconfig :(

That would have been a really nice feature :-)

> 
>>   
>>   config SYS_MALLOC_F_LEN
>> -	default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
>> +	default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000
>> +	default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000
>>   
>>   config SPL_SYS_MALLOC_F_LEN
>> -	default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
>> +	default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000
>> +	default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000
>>   
>>   config TPL_SYS_MALLOC_F_LEN
>> -	default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
>> +	default 0x0800 if CUSTOM_SYS_INIT_SP_ADDR = 0x63f00000
>> +	default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x03f00000
>>   
>>   config TEXT_BASE
>> -	default 0x00200000 if ARM64
>> +	default 0x60200000 if SPL_TEXT_BASE = 0x60000000
>> +	default 0x00200000 if SPL_TEXT_BASE = 0x00000000
>>   
>>   config SPL_TEXT_BASE
>> -	default 0x0 if ARM64
>> +	default 0x60000000 if ROCKCHIP_RK3036 || ROCKCHIP_RK3066 || \
>> +			      ROCKCHIP_RK3128 || ROCKCHIP_RK3188 || \
>> +			      ROCKCHIP_RK322X || ROCKCHIP_RV1108
> 
> If applicable to all ARMv7 SoCs, maybe
> 
> if CPU_V7A
> 
> would be more future-proof?

Unfortunately that does not seem to be the case, most new RK SoCs seem
to use 0x0 as DRAM base, with RK3576 being the odd one, or possible
start of a new trend.

Following ARMv7 SoCs seem to use 0x0 as DRAM base:
- RK3288
- RK3506
- RV1103B
- RV1106
- RV1126

For the RK3506 I have been playing with recently the OP-TEE (for psci)
is instead placed at start of DRAM and SPL must be put somewhere else,
vendor place it at 63 MiB offset, I decided to put SPL at 0.5 MiB
instead of 0x0, so that could require a few more default lines :-S

Regards,
Jonas

> 
> Cheers,
> Quentin