[PATCH v2 05/26] drivers: clk: agilex5: Set PLL to asynchronous mode

[Chee, Tien Fong]

-----Original Message-----
From: alif.zakuan.yuslaimi at intel.com <alif.zakuan.yuslaimi at intel.com> 
Sent: Tuesday, February 18, 2025 4:35 PM
To: u-boot at lists.denx.de
Cc: Marek Vasut <marex at denx.de>; Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>; Chee, Tien Fong <tien.fong.chee at altera.com>; Yuslaimi, Alif Zakuan <alif.zakuan.yuslaimi at altera.com>; Meng, Tingting <tingting.meng at altera.com>; Ng, Boon Khai <boon.khai.ng at altera.com>; Hea, Kok Kiang <kok.kiang.hea at altera.com>; Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at intel.com>; Zamri, Muhammad Hazim Izzat <muhammad.hazim.izzat.zamri at altera.com>
Subject: [PATCH v2 05/26] drivers: clk: agilex5: Set PLL to asynchronous mode

From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at intel.com>

PLL frequency would overshoot from the original target in synchronous mode during low VCC voltage condition.

To resolve this issue, PLL is set to run on asynchronous mode instead of enabling synchronous mode in the clock driver.

Signed-off-by: Muhammad Hazim Izzat Zamri <muhammad.hazim.izzat.zamri at altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
---
 drivers/clk/altera/clk-agilex5.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c
index a284b562486..fb1e72ffc5c 100644
--- a/drivers/clk/altera/clk-agilex5.c
+++ b/drivers/clk/altera/clk-agilex5.c
@@ -72,15 +72,6 @@ static const struct {
 	u32 val;
 	u32 mask;
 } membus_pll[] = {
-	{
-		MEMBUS_CLKSLICE_REG,
-		/*
-		 * BIT[7:7]
-		 * Enable source synchronous mode
-		 */
-		BIT(7),
-		BIT(7)
-	},
 	{
 		MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG,
 		/*
--
2.25.1

Reviewed-by: Tien Fong Chee <tien.fong.chee at altera.com>

Best regards,
Tien Fong