[PATCH v2 06/26] arm: socfpga: agilex5: Add warm reset mask for Agilex5

[Chee, Tien Fong]

-----Original Message-----
From: alif.zakuan.yuslaimi at intel.com <alif.zakuan.yuslaimi at intel.com> 
Sent: Tuesday, February 18, 2025 4:35 PM
To: u-boot at lists.denx.de
Cc: Marek Vasut <marex at denx.de>; Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>; Chee, Tien Fong <tien.fong.chee at altera.com>; Yuslaimi, Alif Zakuan <alif.zakuan.yuslaimi at altera.com>; Meng, Tingting <tingting.meng at altera.com>; Ng, Boon Khai <boon.khai.ng at altera.com>; Hea, Kok Kiang <kok.kiang.hea at altera.com>; Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at intel.com>
Subject: [PATCH v2 06/26] arm: socfpga: agilex5: Add warm reset mask for Agilex5

From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at intel.com>

There are 5 L4 watchdogs and one SDM triggered warm reset bit in Agilex5 reset manager "stat" register where bit 16:20 for L4 watchdogs. Assigning value 1 to these bits in the register address will initiate SDM to trigger warm reset.

Introducing new warm reset mask for Agilex5 to trigger warm reset to all five L4 watchdogs.

Signed-off-by: Tien Fong Chee <tien.fong.chee at altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
---
 arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
index c8bb727aa2b..058fdd6e548 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  *  Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
+ *  Copyright (C) 2025 Altera Corporation <www.altera.com>
  */
 
 #ifndef _RESET_MANAGER_SOC64_H_
@@ -23,14 +24,20 @@ void socfpga_bridges_reset(int enable);
 #define RSTMGR_BRGMODRST_FPGA2SOC_MASK	0x00000004
 
 /* SDM, Watchdogs and MPU warm reset mask */
-#define RSTMGR_STAT_SDMWARMRST		BIT(1)
+#define RSTMGR_STAT_SDMWARMRST		0x2
 #define RSTMGR_STAT_MPU0RST_BITPOS	8
 #define RSTMGR_STAT_L4WD0RST_BITPOS	16
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define RSTMGR_STAT_L4WD0RST_BIT	0x1F0000
+#define RSTMGR_L4WD_MPU_WARMRESET_MASK	(RSTMGR_STAT_SDMWARMRST | \
+		RSTMGR_STAT_L4WD0RST_BIT)
+#else
 #define RSTMGR_L4WD_MPU_WARMRESET_MASK	(RSTMGR_STAT_SDMWARMRST | \
 		GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \
 			RSTMGR_STAT_MPU0RST_BITPOS) | \
 		GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \
 			RSTMGR_STAT_L4WD0RST_BITPOS))
+#endif
 
 /*
  * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
--
2.25.1

Reviewed-by: Tien Fong Chee <tien.fong.chee at altera.com>

Best regards,
Tien Fong