[PATCH 1/2] net: dwc_eth_qos_rockchip: Fix disable of RX/TX delay for RK356x

[Kever Yang]

On 2025/2/10 07:27, Jonas Karlman wrote:
> When rgmii-rxid/txid/id phy-mode is used the MAC should not add RX
> and/or TX delay. Currently RX/TX delay is configured as enabled using
> zero as delay value for the rgmii-rxid/txid/id modes.
>
> Change to disable RX and/or TX delay and using zero as delay value.
>
> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/net/dwc_eth_qos_rockchip.c | 7 +++++--
>   1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c
> index 9fc8c686b889..3e10e07403c1 100644
> --- a/drivers/net/dwc_eth_qos_rockchip.c
> +++ b/drivers/net/dwc_eth_qos_rockchip.c
> @@ -46,6 +46,10 @@ struct rockchip_platform_data {
>   #define GRF_BIT(nr)	(BIT(nr) | BIT((nr) + 16))
>   #define GRF_CLR_BIT(nr)	(BIT((nr) + 16))
>   
> +#define DELAY_ENABLE(soc, tx, rx) \
> +	(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
> +	 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
> +
>   #define RK3568_GRF_GMAC0_CON0		0x0380
>   #define RK3568_GRF_GMAC0_CON1		0x0384
>   #define RK3568_GRF_GMAC1_CON0		0x0388
> @@ -85,8 +89,7 @@ static int rk3568_set_to_rgmii(struct udevice *dev,
>   
>   	regmap_write(data->grf, con1,
>   		     RK3568_GMAC_PHY_INTF_SEL_RGMII |
> -		     RK3568_GMAC_RXCLK_DLY_ENABLE |
> -		     RK3568_GMAC_TXCLK_DLY_ENABLE);
> +		     DELAY_ENABLE(RK3568, tx_delay, rx_delay));
>   
>   	return 0;
>   }