[PATCH] pinctrl: rockchip: rk3328: Fix pinmux for GPIO2-B and GPIO3-B pins

[Kever Yang]

On 2025/1/7 05:39, Jonas Karlman wrote:
> The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width,
> correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is
> recalculated so it remain unchanged. Add missing GPIO3-B1 to GPIO3-B7
> pinmux data to rk3328_mux_recalced_data as mux register offset for these
> pins does not follow rockchip convention.
>
> This matches changes in following Linux commits:
> - e8448a6c817c ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins")
> - 5ef6914e0bf5 ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO3-B pins")
> - 128f71fe014f ("pinctrl: rockchip: correct RK3328 iomux width flag for GPIO2-B pins")
>
> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
>   drivers/pinctrl/rockchip/pinctrl-rk3328.c | 59 ++++++++++++++++++++---
>   1 file changed, 52 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c
> index 47c2e923a1bb..dd0dc2eff270 100644
> --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c
> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c
> @@ -14,23 +14,68 @@
>   
>   static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
>   	{
> -		.num = 2,
> -		.pin = 12,
> -		.reg = 0x24,
> -		.bit = 8,
> -		.mask = 0x3
> -	}, {
> +		/* gpio2_b7_sel */
>   		.num = 2,
>   		.pin = 15,
>   		.reg = 0x28,
>   		.bit = 0,
>   		.mask = 0x7
>   	}, {
> +		/* gpio2_c7_sel */
>   		.num = 2,
>   		.pin = 23,
>   		.reg = 0x30,
>   		.bit = 14,
>   		.mask = 0x3
> +	}, {
> +		/* gpio3_b1_sel */
> +		.num = 3,
> +		.pin = 9,
> +		.reg = 0x44,
> +		.bit = 2,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b2_sel */
> +		.num = 3,
> +		.pin = 10,
> +		.reg = 0x44,
> +		.bit = 4,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b3_sel */
> +		.num = 3,
> +		.pin = 11,
> +		.reg = 0x44,
> +		.bit = 6,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b4_sel */
> +		.num = 3,
> +		.pin = 12,
> +		.reg = 0x44,
> +		.bit = 8,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b5_sel */
> +		.num = 3,
> +		.pin = 13,
> +		.reg = 0x44,
> +		.bit = 10,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b6_sel */
> +		.num = 3,
> +		.pin = 14,
> +		.reg = 0x44,
> +		.bit = 12,
> +		.mask = 0x3
> +	}, {
> +		/* gpio3_b7_sel */
> +		.num = 3,
> +		.pin = 15,
> +		.reg = 0x44,
> +		.bit = 14,
> +		.mask = 0x3
>   	},
>   };
>   
> @@ -275,7 +320,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
>   	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
>   	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
>   	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
> -			     IOMUX_WIDTH_3BIT,
> +			     IOMUX_8WIDTH_2BIT,
>   			     IOMUX_WIDTH_3BIT,
>   			     0),
>   	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",