[PATCH 05/12] arm: Support running U-Boot as a coreboot payload on ARM64

[Stephen Boyd]

Add a 'coreboot' cpu to armv8 that looks for the coreboot table near the
top of the 4G address space.

Signed-off-by: Stephen Boyd <swboyd at chromium.org>
---
 arch/arm/Kconfig                     |  2 ++
 arch/arm/cpu/armv8/Makefile          |  1 +
 arch/arm/cpu/armv8/coreboot/Kconfig  | 22 +++++++++++++
 arch/arm/cpu/armv8/coreboot/Makefile |  4 +++
 arch/arm/cpu/armv8/coreboot/cpu.c    | 46 ++++++++++++++++++++++++++++
 arch/arm/include/asm/global_data.h   |  3 ++
 6 files changed, 78 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/coreboot/Kconfig
 create mode 100644 arch/arm/cpu/armv8/coreboot/Makefile
 create mode 100644 arch/arm/cpu/armv8/coreboot/cpu.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 314916527c9e..027e2a31259c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2354,6 +2354,8 @@ source "arch/arm/cpu/armv7/Kconfig"
 
 source "arch/arm/cpu/armv8/Kconfig"
 
+source "arch/arm/cpu/armv8/coreboot/Kconfig"
+
 source "arch/arm/mach-imx/Kconfig"
 
 source "arch/arm/mach-nexell/Kconfig"
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index b4126c61df15..39258a07db6c 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -48,3 +48,4 @@ obj-$(CONFIG_ARMV8_CE_SHA1) += sha1_ce_glue.o sha1_ce_core.o
 obj-$(CONFIG_ARMV8_CE_SHA256) += sha256_ce_glue.o sha256_ce_core.o
 
 obj-$(CONFIG_SYSINFO_SMBIOS) += sysinfo.o
+obj-$(CONFIG_SYS_COREBOOT) += coreboot/
diff --git a/arch/arm/cpu/armv8/coreboot/Kconfig b/arch/arm/cpu/armv8/coreboot/Kconfig
new file mode 100644
index 000000000000..9392d941df02
--- /dev/null
+++ b/arch/arm/cpu/armv8/coreboot/Kconfig
@@ -0,0 +1,22 @@
+config SYS_COREBOOT
+	bool "Support for booting u-boot as a coreboot payload"
+	imply SCSI
+	imply SCSI_AHCI
+	imply AHCI_PCI
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply USB
+	imply USB_EHCI_HCD
+	imply USB_XHCI_HCD
+	imply USB_STORAGE
+	imply USB_KEYBOARD
+	imply ETH_DESIGNWARE
+	imply RTL8169
+	imply CMD_CBFS
+	imply FS_CBFS
+	imply CBMEM_CONSOLE
+	imply USE_PREBOOT
+	select SYSINFO
+	imply SYSINFO_EXTRA
diff --git a/arch/arm/cpu/armv8/coreboot/Makefile b/arch/arm/cpu/armv8/coreboot/Makefile
new file mode 100644
index 000000000000..0eca9ff05900
--- /dev/null
+++ b/arch/arm/cpu/armv8/coreboot/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += cpu.o
+
diff --git a/arch/arm/cpu/armv8/coreboot/cpu.c b/arch/arm/cpu/armv8/coreboot/cpu.c
new file mode 100644
index 000000000000..e133656858a9
--- /dev/null
+++ b/arch/arm/cpu/armv8/coreboot/cpu.c
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <cb_sysinfo.h>
+#include <linux/errno.h>
+#include <linux/sizes.h>
+#include <log.h>
+
+static long detect_coreboot_table_at(ulong start, ulong size)
+{
+	u32 *ptr, *end;
+
+	size /= 4;
+	for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
+		if (*ptr == 0x4f49424c) /* "LBIO" */
+			return (long)ptr;
+	}
+
+	return -ENOENT;
+}
+
+long locate_coreboot_table(void)
+{
+	long addr;
+
+	/*
+	 * We look for LBIO somewhere inside the CBMEM arena, which is
+	 * typically at the top of the first 4G of RAM.
+	 */
+	addr = detect_coreboot_table_at(SZ_4G - SZ_8M, SZ_8M);
+	if (addr < 0)
+		return -ENOENT;
+
+	debug("Located coreboot table at %#lx\n", addr);
+	return addr;
+}
+
+int arch_cpu_init(void)
+{
+	int ret;
+
+	ret = get_coreboot_info(&lib_sysinfo);
+	if (ret != 0)
+		debug("Failed to parse coreboot tables.\n");
+
+	return 0;
+}
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 45401d5e3c8a..70299aec2df4 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -108,6 +108,9 @@ struct arch_global_data {
 #ifdef CONFIG_SMBIOS
 	ulong smbios_start;		/* Start address of SMBIOS table */
 #endif
+#ifdef CONFIG_SYS_COREBOOT
+	ulong coreboot_table;		/* Address of coreboot table */
+#endif
 };
 
 #include <asm-generic/global_data.h>
-- 
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