[PATCH 10/17] spl: Align FDT load address

[Heinrich Schuchardt]

On 2/24/25 06:55, Sam Edwards wrote:
> While the image size is generally a multiple of 8 bytes, this is not
> actually guaranteed; some linkers (like LLD) may shave a few bytes off
> of the end of output sections if there are no content bytes there. Since
> libfdt imposes a hard rule of 8-byte alignment, make the SPL also be
> explicit about the alignment when loading the FDT.
>
> Signed-off-by: Sam Edwards <CFSworks at gmail.com>
> ---
>   common/spl/spl_fit.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
> index 49b4df60560..86506d6905c 100644
> --- a/common/spl/spl_fit.c
> +++ b/common/spl/spl_fit.c
> @@ -397,7 +397,7 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image,
>   	 * Use the address following the image as target address for the
>   	 * device tree.
>   	 */
> -	image_info.load_addr = spl_image->load_addr + spl_image->size;
> +	image_info.load_addr = ALIGN(spl_image->load_addr + spl_image->size, 8);

We want to keep the SPL code size as small as possible as on many
platforms it is restricted to the cache size.

Can't we fix this linker issue in the linker script by properly aligning
the SPL image end address?

Best regards

Heinrich

>
>   	/* Figure out which device tree the board wants to use */
>   	node = spl_fit_get_image_node(ctx, FIT_FDT_PROP, index++);