[PATCH v5 3/7] clk/qcom: add initial clock driver for ipq9574
Caleb Connolly
caleb.connolly at linaro.org
Tue Feb 25 12:42:43 CET 2025
Hiya,
On 2/25/25 06:52, Varadarajan Narayanan wrote:
> Add initial set of clocks and resets for enabling U-Boot on ipq9574
> based RDP platforms.
>
> Reviewed-by: Caleb Connolly <caleb.connolly at linaro.org>
> Signed-off-by: Varadarajan Narayanan <quic_varada at quicinc.com>
> ---
> v3: Use gate clk framework
>
> v2: Combined driver file and makefile/kconfig changes into one patch
> ---
> drivers/clk/qcom/Kconfig | 8 +++
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/clock-ipq9574.c | 109 +++++++++++++++++++++++++++++++
> drivers/clk/qcom/clock-qcom.h | 1 +
> 4 files changed, 119 insertions(+)
> create mode 100644 drivers/clk/qcom/clock-ipq9574.c
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index cb867acc48c..3ea01f3c969 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -31,6 +31,14 @@ config CLK_QCOM_IPQ4019
> on the Snapdragon IPQ4019 SoC. This driver supports the clocks
> and resets exposed by the GCC hardware block.
>
> +config CLK_QCOM_IPQ9574
> + bool "Qualcomm IPQ9574 GCC"
> + select CLK_QCOM
> + help
> + Say Y here to enable support for the Global Clock Controller
> + on the Snapdragon IPQ9574 SoC. This driver supports the clocks
> + and resets exposed by the GCC hardware block.
> +
> config CLK_QCOM_QCM2290
> bool "Qualcomm QCM2290 GCC"
> select CLK_QCOM
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 1bc0f15005b..e13fc8c1071 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_CLK_QCOM_SDM845) += clock-sdm845.o
> obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o
> obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o
> obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o
> +obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o
> obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
> obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
> obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o
> diff --git a/drivers/clk/qcom/clock-ipq9574.c b/drivers/clk/qcom/clock-ipq9574.c
> new file mode 100644
> index 00000000000..fff87036dd0
> --- /dev/null
> +++ b/drivers/clk/qcom/clock-ipq9574.c
> @@ -0,0 +1,109 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Clock drivers for Qualcomm ipq9574
> + *
> + * (C) Copyright 2025 Linaro Ltd.
> + */
> +
> +#include <linux/types.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <linux/delay.h>
> +#include <asm/io.h>
> +#include <linux/bug.h>
> +#include <linux/bitops.h>
> +#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> +#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
> +
> +#include "clock-qcom.h"
> +
> +#define GCC_BLSP1_AHB_CBCR 0x1004
> +#define GCC_BLSP1_UART3_APPS_CMD_RCGR 0x402C
> +#define GCC_BLSP1_UART3_APPS_CBCR 0x4054
> +
> +#define GCC_SDCC1_APPS_CBCR 0x3302C
> +#define GCC_SDCC1_AHB_CBCR 0x33034
> +#define GCC_SDCC1_APPS_CMD_RCGR 0x33004
> +#define GCC_SDCC1_ICE_CORE_CBCR 0x33030
> +
> +static ulong ipq9574_set_rate(struct clk *clk, ulong rate)
> +{
> + struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +
> + switch (clk->id) {
> + case GCC_BLSP1_UART3_APPS_CLK:
> + clk_rcg_set_rate_mnd(priv->base, GCC_BLSP1_UART3_APPS_CMD_RCGR,
> + 0, 144, 15625, CFG_CLK_SRC_GPLL0, 16);
> + return rate;
> + case GCC_SDCC1_APPS_CLK:
> + clk_rcg_set_rate_mnd(priv->base, GCC_SDCC1_APPS_CMD_RCGR,
> + 11, 0, 0, CFG_CLK_SRC_GPLL2, 16);
> + return rate;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static const struct gate_clk ipq9574_clks[] = {
> + GATE_CLK(GCC_BLSP1_UART3_APPS_CLK, 0x4054, 0x00000001),
> + GATE_CLK(GCC_BLSP1_AHB_CLK, 0x1004, 0x00000001),
> + GATE_CLK(GCC_SDCC1_AHB_CLK, 0x33034, 0x00000001),
> + GATE_CLK(GCC_SDCC1_APPS_CLK, 0x3302C, 0x00000001),
> + GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x33030, 0x00000001),
> +};
> +
> +static int ipq9574_enable(struct clk *clk)
> +{
> + struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> +
> + debug("%s: clk %s\n", __func__, ipq9574_clks[clk->id].name);
> +
> + switch (clk->id) {
> + case GCC_BLSP1_UART3_APPS_CLK:
> + qcom_gate_clk_en(priv, GCC_BLSP1_UART3_APPS_CLK);
> + break;
> + case GCC_BLSP1_AHB_CLK:
> + qcom_gate_clk_en(priv, GCC_BLSP1_AHB_CLK);
> + break;
> + case GCC_SDCC1_AHB_CLK:
> + qcom_gate_clk_en(priv, GCC_SDCC1_AHB_CLK);
> + break;
> + case GCC_SDCC1_APPS_CLK:
> + qcom_gate_clk_en(priv, GCC_SDCC1_APPS_CLK);
> + break;
> + case GCC_SDCC1_ICE_CORE_CLK:
> + qcom_gate_clk_en(priv, GCC_SDCC1_ICE_CORE_CLK);
> + break;
> + default:
> + return -EINVAL;
> + }
Last nitpick here, the reason I proposed using the gate_clk API is
because it lets you drop this switch/case. Since you don't do any prep
before enabling these clocks you can just call
qcom_gate_clk_en(priv, clk->id);
With that fixed
Reviewed-by: Caleb Connolly <caleb.connolly at linaro.org>
Thanks for sticking with me on this.
Kind regards,
> +
> + return 0;
> +}
> +
> +static const struct qcom_reset_map ipq9574_gcc_resets[] = {
> + [GCC_SDCC_BCR] = { 0x33000 },
> +};
> +
> +static struct msm_clk_data ipq9574_gcc_data = {
> + .resets = ipq9574_gcc_resets,
> + .num_resets = ARRAY_SIZE(ipq9574_gcc_resets),
> + .enable = ipq9574_enable,
> + .set_rate = ipq9574_set_rate,
> +};
> +
> +static const struct udevice_id gcc_ipq9574_of_match[] = {
> + {
> + .compatible = "qcom,ipq9574-gcc",
> + .data = (ulong)&ipq9574_gcc_data,
> + },
> + { }
> +};
> +
> +U_BOOT_DRIVER(gcc_ipq9574) = {
> + .name = "gcc_ipq9574",
> + .id = UCLASS_NOP,
> + .of_match = gcc_ipq9574_of_match,
> + .bind = qcom_cc_bind,
> + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
> +};
> diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
> index ff336dea39c..e038dc421ec 100644
> --- a/drivers/clk/qcom/clock-qcom.h
> +++ b/drivers/clk/qcom/clock-qcom.h
> @@ -11,6 +11,7 @@
> #define CFG_CLK_SRC_CXO (0 << 8)
> #define CFG_CLK_SRC_GPLL0 (1 << 8)
> #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8)
> +#define CFG_CLK_SRC_GPLL2 (2 << 8)
> #define CFG_CLK_SRC_GPLL9 (2 << 8)
> #define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
> #define CFG_CLK_SRC_GPLL6 (4 << 8)
--
Caleb (they/them)
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