[PATCH 2/2] sunxi: sun50i_h6: clock: fix PLL_PERIPH0 rate calculation

[Jernej Škrabec]

Dne sreda, 26. februar 2025 ob 12:37:12 Srednjeevropski standardni čas je Andre Przywara napisal(a):
> On the Allwinner D1/R528/T113-s3 SoCs (NCAT2) the factors encoded in
> the PLL register describe the doubled clock rate, as in the other SoCs.
> 
> Correct for that by always dividing the calculated rate by 2, except on
> the H6, where we need a divisor of 4 (no change here).
> 
> This corrects the PERIPH0 clock rate as read by the MMC driver, and
> actually doubles the MMC performance on those NCAT2 chips.
> 
> Signed-off-by: Andre Przywara <andre.przywara at arm.com>
> Reported-by: Kuba Szczodrzyński <kuba at szczodrzynski.pl>

Reviewed-by: Jernej Skrabec <jernej.skrabec at gmail.com>

Best regards,
Jernej