[PATCH 2/5] riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init

[Leo Liang]

On Fri, Jun 06, 2025 at 04:28:01AM +0000, Yao Zi wrote:
> C910 cores integrated in TH1520 SoC provide various customized CSRs for
> configuring core behavior, including cache coherency and timing, branch
> predication, and clock gating for internal components.
> 
> This patch sets them up for efficient operation and satisfying
> requirements of an SMP system.
> 
> Signed-off-by: Yao Zi <ziyao at disroot.org>
> ---
>  arch/riscv/cpu/th1520/spl.c | 83 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 83 insertions(+)

Reviewed-by: Leo Yu-Chi Liang <ycliang at andestech.com>