[PATCH v5 1/4] mach-k3: use minimal MMU table for all k3

[Anshul Dalal]

This patch replaces the existing MMU table with a minimal bootable table
(at least till SPL) that could be modified at runtime as per the
device-tree and the CONFIG_K3_*_LOAD_ADDR.

The 128MiB region starting from SPL_TEXT_BASE is mapped for use by the
A-core SPL. 128MiB provides enough space for future use cases such as
falcon boot from the A-Core SPL etc.

Signed-off-by: Anshul Dalal <anshuld at ti.com>
---
 arch/arm/mach-k3/arm64/arm64-mmu.c | 38 ++++++++++++------------------
 1 file changed, 15 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-k3/arm64/arm64-mmu.c b/arch/arm/mach-k3/arm64/arm64-mmu.c
index 0e07b1b7ce0..5c29df4fe6f 100644
--- a/arch/arm/mach-k3/arm64/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64/arm64-mmu.c
@@ -12,41 +12,33 @@
 #include <asm/system.h>
 #include <asm/armv8/mmu.h>
 
-struct mm_region k3_mem_map[] = {
-	{
+/* We need extra 5 entries for:
+ * SoC peripherals, flash, atf-carveout, tee-carveout and the sentinel value.
+ */
+#define K3_MMU_REGIONS_COUNT ((CONFIG_NR_DRAM_BANKS) + 5)
+
+struct mm_region k3_mem_map[K3_MMU_REGIONS_COUNT] = {
+	{ /* SoC Peripherals */
 		.virt = 0x0UL,
 		.phys = 0x0UL,
 		.size = 0x80000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0x80000000UL,
-		.phys = 0x80000000UL,
-		.size = 0x1e780000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0xa0000000UL,
-		.phys = 0xa0000000UL,
-		.size = 0x60000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
-		.virt = 0x880000000UL,
-		.phys = 0x880000000UL,
-		.size = 0x80000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_INNER_SHARE
-	}, {
+	}, { /* Flash peripherals */
 		.virt = 0x500000000UL,
 		.phys = 0x500000000UL,
 		.size = 0x380000000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		/* List terminator */
+	}, { /* Map SPL load region and the next 128MiB as cacheable */
+		.virt = CONFIG_SPL_TEXT_BASE,
+		.phys = CONFIG_SPL_TEXT_BASE,
+		.size = SZ_128M,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, { /* List terminator */
 		0,
 	}
 };
-- 
2.49.0