[PATCH v5 3/4] mach-k3: add dynamic mmu fixups for SPL stage

[Anshul Dalal]

On platforms with spl splash support such as 62p and 62x
(CONFIG_VIDEO=y), the top of DDR is reserved for the framebuffer.

The size of the framebuffer is computed at runtime by video_reserve.
During the MMU configuration an entry corresponding to the framebuffer
should be dynamically created to properly allocate the required space
for the framebuffer.

Therefore this patch adds k3_spl_mem_map_init which adds the required
MMU entry by querying the gd after the framebuffer size has been
computed in spl_reserve_video_from_ram_top.

Signed-off-by: Anshul Dalal <anshuld at ti.com>
---
 arch/arm/mach-k3/arm64/arm64-mmu.c | 13 ++++++++++++-
 arch/arm/mach-k3/common.c          | 17 ++++++++++++++---
 2 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-k3/arm64/arm64-mmu.c b/arch/arm/mach-k3/arm64/arm64-mmu.c
index 49dd6fcb23b..b1b287f2114 100644
--- a/arch/arm/mach-k3/arm64/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64/arm64-mmu.c
@@ -131,6 +131,13 @@ static int k3_setup_extra_mem_banks(unsigned int *map_idx)
 	return 0;
 }
 
+static void k3_spl_mem_map_init(unsigned int *map_idx)
+{
+	if (CONFIG_IS_ENABLED(VIDEO))
+		k3_mmu_add_cachable_entry(gd_video_bottom(), gd_video_top(),
+					  map_idx);
+}
+
 static int k3_uboot_mem_map_init(unsigned int *map_idx)
 {
 	int ret;
@@ -159,7 +166,11 @@ int k3_mem_map_init(void)
 
 	map_idx++;
 
-	ret = k3_uboot_mem_map_init(&map_idx);
+	if (xpl_phase() == PHASE_SPL)
+		k3_spl_mem_map_init(&map_idx);
+	else
+		ret = k3_uboot_mem_map_init(&map_idx);
+
 	if (ret)
 		return ret;
 
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index fc230f180d0..e72413b9803 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -32,6 +32,7 @@
 #include <dm/device-internal.h>
 
 #include <asm/arch/k3-qos.h>
+#include <mach/k3-ddr.h>
 
 struct ti_sci_handle *get_ti_sci_handle(void)
 {
@@ -224,16 +225,26 @@ void spl_enable_cache(void)
 
 	dram_init();
 
-	/* reserve TLB table */
-	gd->arch.tlb_size = PGTABLE_SIZE;
-
 	gd->ram_top += get_effective_memsize();
+	/* keep ram_top in the 32-bit address space */
+	if (gd->ram_top >= 0x100000000)
+		gd->ram_top = (phys_addr_t)0x100000000;
+
 	gd->relocaddr = gd->ram_top;
 
 	ret = spl_reserve_video_from_ram_top();
 	if (ret)
 		panic("Failed to reserve framebuffer memory (%d)\n", ret);
 
+	if (IS_ENABLED(CONFIG_ARM64)) {
+		ret = k3_mem_map_init();
+		if (ret)
+			panic("Failed to setup MMU table (%d)\n", ret);
+	}
+
+	/* reserve TLB table */
+	gd->arch.tlb_size = PGTABLE_SIZE;
+
 	gd->arch.tlb_addr = gd->relocaddr - gd->arch.tlb_size;
 	gd->arch.tlb_addr &= ~(0x10000 - 1);
 	debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
-- 
2.49.0