[PATCH] configs: Relocate malloc and bss address

[Maniyam, Dinesh]

Hi

> -----Original Message-----
> From: Peng Fan <peng.fan at oss.nxp.com>
> Sent: Friday, 11 July 2025 11:54 am
> To: Maniyam, Dinesh <dinesh.maniyam at altera.com>
> Cc: u-boot at lists.denx.de; Marek <marex at denx.de>; Simon
> <simon.k.r.goldschmidt at gmail.com>; Simon Glass <sjg at chromium.org>; Tom
> Rini <trini at konsulko.com>; Chee, Tien Fong <tien.fong.chee at altera.com>;
> Hea, Kok Kiang <kok.kiang.hea at altera.com>; Ng, Boon Khai
> <boon.khai.ng at altera.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi at altera.com>; Lim, Jit Loon <jit.loon.lim at altera.com>;
> Dinesh Maniyam <dinesh.maniyam at intel.com>
> Subject: Re: [PATCH] configs: Relocate malloc and bss address
> 
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> On Thu, Jul 10, 2025 at 12:12:53PM +0800, dinesh.maniyam at altera.com
> wrote:
> >From: Dinesh Maniyam <dinesh.maniyam at intel.com>
> >
> 
> Nit, update subject with socfpga_agilex5: config:
> 

Noted. I will update it.

> >With Inline ECC enabled, the bottom 1/8 of DDR is reserved for ECC
> >parity bits and must not be used for general data address allocation.
> >Previously, the SPL bss and malloc addresses were allocated inside this
> >ECC parity region if the DDR size is 1GB.
> >
> >This caused ECC hardware to detect stale or invalid parity bits,
> >leading to data correction attempts and DMA polling hangs or failures.
> >
> >Fix this by relocating the malloc and bss to the usable 7/8 region of
> >DDR and is fully ECC-safe.
> >
> >This change ensures reliable ddr address operation and prevents
> >unintended memory corruption.
> >
> >Signed-off-by: Dinesh Maniyam <dinesh.maniyam at intel.com>
> >---
> > configs/socfpga_agilex5_defconfig | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> >diff --git a/configs/socfpga_agilex5_defconfig
> >b/configs/socfpga_agilex5_defconfig
> >index 4ac0a5d9b99..01c5ac88015 100644
> >--- a/configs/socfpga_agilex5_defconfig
> >+++ b/configs/socfpga_agilex5_defconfig
> >@@ -12,7 +12,7 @@
> CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk"
> > CONFIG_DM_RESET=y
> > CONFIG_SPL_STACK=0x7d000
> > CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
> >-CONFIG_SPL_BSS_START_ADDR=0xbff00000
> >+CONFIG_SPL_BSS_START_ADDR=0x9ff00000
> 
> Commit says bottom is reserved, but here bss start is moved to low address.
> ECC area is at top area?
> 
> Regards,
> Peng

The idea here is to move the bss_start_addr to DDR base address + 512MB. 
The ECC-reserved area remains at the lower end of DDR, and since
Agilex 5 requires a minimum DDR size of 1GB, this memory layout is safe.

This approach maintains consistency with the existing memory layout logic defined for previous SoCs in:
include/configs/socfpga_soc64_common.h

Regards
Dinesh