[PATCH v2] spi: cadence_qspi: Fix odd byte write issue in STIG mode

[Michal Simek]

On 7/15/25 13:19, Prasanth Mantena wrote:
> On 13:51, Prasanth Mantena wrote:
>> On 09:34, Venkatesh Yadav Abbarapu wrote:
>>> Starting from 'commit <8077d296adff> ("spi: cadence-quadspi: Use STIG
>>> mode for all ops with small payload") the utilization of STIG mode
>>> has been implemented for read and write operations involving less
>>> than 8 bytes of data.
>>>
>>> However, following this commit, encountering timeout issues occurs when
>>> writing odd bytes of data in DDR mode, as indicated below:
>>> "jedec_spi_nor flash at 0: flash operation timed out
>>> SF: 3 bytes @ 0x0 Written: ERROR -110"
>>>
>>> To resolve this issue, the number of bytes to write has been updated
>>> specifically for DDR mode.
>>>
>>> Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar at amd.com>
>>> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu at amd.com>
>>> ---
>>> Changes in v2:
>>> -Modified the logic from using modulus and changed to use "logical and"
>>> operator to check the odd bytes.
>>> ---
>>>   drivers/spi/cadence_qspi_apb.c | 3 +++
>>>   1 file changed, 3 insertions(+)
>>>
>>> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
>>> index b579699d2eb..76569a8019b 100644
>>> --- a/drivers/spi/cadence_qspi_apb.c
>>> +++ b/drivers/spi/cadence_qspi_apb.c
>>> @@ -554,6 +554,9 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv,
>>>   	void *reg_base = priv->regbase;
>>>   	u8 opcode;
>>>   
>>> +	if (priv->dtr)
>>> +		txlen += txlen & 1;
>>> +
>>
>> Hi Venkatesh,
>>
>> 1> Is this not a generic problem, having a DTR write in stig mode. If so,
>> shouldn't this be handled at the spi-nor core level.
>>
>> 2> You are just increasing the number of bytes here, aren't we writing
>> an unwanted extra data ? Where did we pad the buffer ?
>>
> 
> NACK. Considering the issues that this can cause, referring the above comments.
> Michal Simek, my request is to please wait for some comment / review for
> the common code like this, considering this merge was quick.

I realized that this affects also other users late. Sorry about it. Feel free to 
send revert or fix.

Thanks,
Michal