[PATCH 0/3] Update riscv's SYS_BOOTM_LEN to the most commonly used value.

[Leo Liang]

On Wed, Jul 16, 2025 at 11:00:15AM -0600, Tom Rini wrote:
> [EXTERNAL MAIL]

> Date: Wed, 16 Jul 2025 11:00:15 -0600
> From: Tom Rini <trini at konsulko.com>
> To: E Shattow <e at freeshell.de>
> Cc: Michal Simek <michal.simek at amd.com>, Martin Herren
>  <sputnik at on-the-web.ch>, u-boot at lists.denx.de, Andreas Schwab
>  <schwab at suse.de>, Anup Patel <anup at brainfault.org>, Atish Patra
>  <atishp at atishpatra.org>, Bin Meng <bmeng.cn at gmail.com>, "Chia-Wei, Wang"
>  <chiawei_wang at aspeedtech.com>, Conor Dooley <conor.dooley at microchip.com>,
>  Cyril Jean <cyril.jean at microchip.com>, Green Wan <green.wan at sifive.com>,
>  Hal Feng <hal.feng at starfivetech.com>, Heinrich Schuchardt
>  <xypron.glpk at gmx.de>, Ilias Apalodimas <ilias.apalodimas at linaro.org>,
>  Jerome Forissier <jerome.forissier at linaro.org>, Junhui Liu
>  <junhui.liu at pigmoral.tech>, Kongyang Liu <seashell11234455 at gmail.com>, Leo
>  Yu-Chi Liang <ycliang at andestech.com>, Maksim Kiselev
>  <bigunclemax at gmail.com>, Marek Vasut <marek.vasut+renesas at mailbox.org>,
>  Martin Schwan <m.schwan at phytec.de>, Mattijs Korpershoek
>  <mkorpershoek at kernel.org>, Minda Chen <minda.chen at starfivetech.com>,
>  Padmarao Begari <padmarao.begari at amd.com>, Palmer Dabbelt
>  <palmer at dabbelt.com>, Paul Walmsley <paul.walmsley at sifive.com>, Peter
>  Robinson <pbrobinson at gmail.com>, Rick Chen <rick at andestech.com>, Sean
>  Anderson <seanga2 at gmail.com>, Simon Glass <sjg at chromium.org>, Sumit Garg
>  <sumit.garg at kernel.org>, Thomas Bonnefille
>  <thomas.bonnefille at bootlin.com>, Wei Fu <wefu at redhat.com>, Yao Zi
>  <ziyao at disroot.org>, Yixun Lan <dlan at gentoo.org>, Yuri Zaporozhets
>  <yuriz at vodafonemail.de>
> Subject: Re: [PATCH 0/3] Update riscv's SYS_BOOTM_LEN to the most commonly
>  used value.
> 
> On Tue, Jul 15, 2025 at 06:35:17PM -0700, E Shattow wrote:
> > 
> > 
> > On 7/15/25 04:27, Michal Simek wrote:
> > > 
> > > 
> > > On 7/14/25 15:33, Martin Herren wrote:
> > >>
> > >> The most commonly used SYS_BOOTM_LEN for riscv is 0x4000000 which is
> > >> used in 25 of the current defconfigs.
> > >>
> > >> The previous default config value of 0x800000 was only used in 8
> > >> defconfigs.
> > >>
> > >> This patch sets the default to this value.
> > >>
> > >> Command used to get the stats of the used values on RISCV defconfigs:
> > >>
> > >> ```
> > >> grep -l "CONFIG_RISCV=y" configs/* | \
> > >>   xargs -I {} sh -c "grep -H CONFIG_SYS_BOOTM_LEN {} || echo
> > >> {}:DEFAULT" | \
> > >>   cut -d ':' -f 2 | sort | uniq -c
> > >> ```
> > >>
> > >> Changes in v2:
> > >> - Resubmit using another mail provider to prevent mangling and signature
> > >>    attachement.
> > >>
> > >> Martin Herren (3):
> > >>    riscv: Set SYS_BOOTM_LEN explicitly to 0x800000
> > >>    riscv: Set SYS_BOOTM_LEN default to 0x4000000
> > >>    riscv: Remove default SYS_BOOTM_LEN from defconfig
> > >>
> > >>   boot/Kconfig                            | 2 +-
> > >>   configs/ae350_rv32_defconfig            | 1 -
> > >>   configs/ae350_rv32_falcon_defconfig     | 1 -
> > >>   configs/ae350_rv32_falcon_xip_defconfig | 1 -
> > >>   configs/ae350_rv32_spl_defconfig        | 1 -
> > >>   configs/ae350_rv32_spl_xip_defconfig    | 1 -
> > >>   configs/ae350_rv32_xip_defconfig        | 1 -
> > >>   configs/ae350_rv64_defconfig            | 1 -
> > >>   configs/ae350_rv64_falcon_defconfig     | 1 -
> > >>   configs/ae350_rv64_falcon_xip_defconfig | 1 -
> > >>   configs/ae350_rv64_spl_defconfig        | 1 -
> > >>   configs/ae350_rv64_spl_xip_defconfig    | 1 -
> > >>   configs/ae350_rv64_xip_defconfig        | 1 -
> > >>   configs/ibex-ast2700_defconfig          | 1 -
> > >>   configs/k230_canmv_defconfig            | 1 +
> > >>   configs/microchip_mpfs_icicle_defconfig | 1 +
> > >>   configs/milkv_duo_defconfig             | 1 -
> > >>   configs/qemu-riscv32_defconfig          | 1 -
> > >>   configs/qemu-riscv32_smode_defconfig    | 1 -
> > >>   configs/qemu-riscv32_spl_defconfig      | 1 -
> > >>   configs/qemu-riscv64_defconfig          | 1 -
> > >>   configs/qemu-riscv64_smode_defconfig    | 1 -
> > >>   configs/qemu-riscv64_spl_defconfig      | 1 -
> > >>   configs/sifive_unleashed_defconfig      | 1 -
> > >>   configs/sifive_unmatched_defconfig      | 1 -
> > >>   configs/sipeed_licheerv_nano_defconfig  | 1 -
> > >>   configs/sipeed_maix_bitm_defconfig      | 1 +
> > >>   configs/sipeed_maix_smode_defconfig     | 1 +
> > >>   configs/starfive_visionfive2_defconfig  | 1 -
> > >>   configs/th1520_lpi4a_defconfig          | 1 -
> > >>   configs/xilinx_mbv32_defconfig          | 1 +
> > >>   configs/xilinx_mbv32_smode_defconfig    | 1 +
> > >>   configs/xilinx_mbv64_defconfig          | 1 +
> > >>   configs/xilinx_mbv64_smode_defconfig    | 1 +
> > >>   34 files changed, 9 insertions(+), 26 deletions(-)
> > >>
> > > 
> > > I don't mind with these changes. It is just value which can be changed.
> > > 
> > > Acked-by; Michal Simek <michal.simek at amd.com> # xilinx_mbv
> > > 
> > > Thanks
> > > Michal
> > > 
> > > 
> > 
> > Is there some reason for the value from documentation about the
> > architecture? Or is it arbitrary?
> > 
> > I don't really see the sense in a default value which is simply popular
> > but not founded in an architectural reasoning.
> > 
> > The values do not change often (ever?) so I miss why there is any
> > default at all.
> 
> So, the default for SYS_BOOTM_LEN isn't so much arbitrary as just no
> longer reflective of modern times. It's why there's larger defaults for
> ARM64 for example. Likely RISCV should just also use that as the default
> and platforms with very small amounts of RAM should stick with smaller.
> 
> -- 
> Tom

Hi Martin,

These changes seem reasonable, and I'm fine with them.
If you send a v2 PR incorporating Conor's comment on the first patch,
you may add my Reviewed-by tag.

Best regards,
Leo