[PATCH 09/10] rockchip: rk3576: Disable USB3OTG0 U3 port early

[Jonas Karlman]

The RK3576 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (USBDP PHY).

Some board designs may not use the USBDP PHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.

Change to always disable the USB3OTG0 U3 port early and leave it to the
USBDP PHY driver to re-enable the U3 port when a usb3-phy is described
in the board device tree.

Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
---
 arch/arm/mach-rockchip/rk3576/rk3576.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c
index ba5c94b4b3dd..dc53941ab2f5 100644
--- a/arch/arm/mach-rockchip/rk3576/rk3576.c
+++ b/arch/arm/mach-rockchip/rk3576/rk3576.c
@@ -29,6 +29,9 @@
 #define SGRF_DOMAIN_CON4	0x10
 #define SGRF_DOMAIN_CON5	0x14
 
+#define USB_GRF_BASE		0x2601E000
+#define USB3OTG0_CON1		0x0030
+
 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
 	[BROM_BOOTSOURCE_EMMC] = "/soc/mmc at 2a330000",
 	[BROM_BOOTSOURCE_SD] = "/soc/mmc at 2a310000",
@@ -151,5 +154,8 @@ int arch_cpu_init(void)
 	 */
 	writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
 
+	/* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */
+	writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
+
 	return 0;
 }
-- 
2.50.1