[PATCH 3/3] Add imx8mp-libra-fpsc board
Yannic Moog
Y.Moog at phytec.de
Fri Jul 25 14:26:17 CEST 2025
Hi Benjamin,
please add documentation for this board.
What do you think about putting all the standard boot variables at the beginning
of RAM and LOAD ADDR after that to avoid potential collisions?
See phycore-imx8mm and tauri for reference.
Am Freitag, dem 25.07.2025 um 12:35 +0200 schrieb Benjamin Hahn:
> Add new imx8mp-libra-fpsc board.
> USB is not working yet, as the entry in the upstream devicetree is
> missing.
>
> Signed-off-by: Benjamin Hahn <B.Hahn at phytec.de>
> ---
> arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi | 78 +
> arch/arm/mach-imx/imx8m/Kconfig | 9 +
> board/phytec/imx8mp-libra-fpsc/Kconfig | 16 +
> board/phytec/imx8mp-libra-fpsc/MAINTAINERS | 8 +
> board/phytec/imx8mp-libra-fpsc/Makefile | 10 +
> board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c | 114 ++
> .../phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env | 30 +
> board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c | 1846
> ++++++++++++++++++++
> board/phytec/imx8mp-libra-fpsc/spl.c | 131 ++
> configs/imx8mp-libra-fpsc_defconfig | 170 ++
> include/configs/imx8mp-libra-fpsc.h | 27 +
> 11 files changed, 2439 insertions(+)
>
>
[...]
> diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
> index 74416a788473..2e4b86473c63 100644
> --- a/arch/arm/mach-imx/imx8m/Kconfig
> +++ b/arch/arm/mach-imx/imx8m/Kconfig
> @@ -345,6 +345,14 @@ config TARGET_PHYCORE_IMX8MP
> select IMX8M_LPDDR4
> imply OF_UPSTREAM
>
> +config TARGET_IMX8MP_LIBRA_FPSC
> + bool "PHYTEC Libra FPSC i.MX 8M Plus"
PHYTEC Libra i.MX 8M Plus FPSC
> + select IMX8MP
> + select SUPPORT_SPL
> + select IMX8M_LPDDR4
don't you need imply OF_UPSTREAM here?
> + help
> + i.MX8M Plus Libra is an FPSC SOM based on NXP i.MX8MP.
Libra i.MX 8M Plus FPSC is a SBC based on the NXP i.MX 8M Plus SoC.
> +
> config TARGET_IMX8MM_CL_IOT_GATE
> bool "CompuLab iot-gate-imx8"
> select IMX8MM
> @@ -411,6 +419,7 @@ source "board/msc/sm2s_imx8mp/Kconfig"
> source "board/mntre/imx8mq_reform2/Kconfig"
> source "board/phytec/phycore_imx8mm/Kconfig"
> source "board/phytec/phycore_imx8mp/Kconfig"
> +source "board/phytec/imx8mp-libra-fpsc/Kconfig"
please order alphabetically
> source "board/polyhex/imx8mp_debix_model_a/Kconfig"
> source "board/purism/librem5/Kconfig"
> source "board/ronetix/imx8mq-cm/Kconfig"
>
[...]
> diff --git a/board/phytec/imx8mp-libra-fpsc/MAINTAINERS b/board/phytec/imx8mp-
> libra-fpsc/MAINTAINERS
> new file mode 100644
> index 000000000000..16b18b605e0d
> --- /dev/null
> +++ b/board/phytec/imx8mp-libra-fpsc/MAINTAINERS
> @@ -0,0 +1,8 @@
> +Libra-i.MX 8M Plus
> +M: Teresa Remmet <t.remmet at phytec.de>
> +W:
> https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc/
> +S: Maintained
> +F: arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi
> +F: board/phytec/imx8mp-libra-fpsc/
> +F: configs/imx8mp-libra-fpsc_defconfig
> +F: include/configs/imx8mp-libra-fpsc.h
> diff --git a/board/phytec/imx8mp-libra-fpsc/Makefile b/board/phytec/imx8mp-
> libra-fpsc/Makefile
> new file mode 100644
> index 000000000000..8f956eb2ffbb
> --- /dev/null
> +++ b/board/phytec/imx8mp-libra-fpsc/Makefile
> @@ -0,0 +1,10 @@
> +# SPDX-License-Identifier: GPL-2.0-or-later
> +#
> +# Copyright (C) 2025 PHYTEC Messtechnik GmbH
> +
> +obj-y += imx8mp-libra-fpsc.o
> +
> +ifdef CONFIG_SPL_BUILD
ifdef CONFIG_XPL_BUILD
> +obj-y += spl.o
> +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
> +endif
> diff --git a/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c
> b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c
> new file mode 100644
> index 000000000000..89b3b6f90ecb
> --- /dev/null
> +++ b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c
> @@ -0,0 +1,114 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (C) 2025 PHYTEC Messtechnik GmbH
> + */
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/global_data.h>
> +#include <linux/io.h>
> +#include <asm/mach-imx/boot_mode.h>
> +#include <dwc3-uboot.h>
> +#include <env.h>
> +#include <init.h>
> +#include <fdt_support.h>
> +#include <jffs2/load_kernel.h>
> +#include <miiphy.h>
> +#include <mtd_node.h>
> +#include <usb.h>
> +#include <i2c.h>
> +
> +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION)
> +#include "../common/imx8m_som_detection.h"
> +#endif
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define EEPROM_ADDR 0x51
> +
> +#define TUSB_PORT_POL_CRTL_REG 0xB
> +#define TUSB_CUSTOM_POL BIT(7)
> +#define TUSB_P0_POL BIT(0)
> +
> +/*
> + * WORKAROUND for PCM-937-L 1618.0, 1618.1.
> + * USB HUB TUSB8042A has swapped upstream pin polarity.
> + * Set i2c registers to inform the hub that the lines
> + * are swapped.
> + */
> +void tusb8042a_swap_lines(void)
> +{
> + const u8 pol_swap_val = (TUSB_CUSTOM_POL | TUSB_P0_POL);
> + const int addr = 0x44;
> + struct udevice *dev = 0;
> + int ret = i2c_get_chip_for_busnum(2, addr, 1, &dev);
> +
> + if (!ret)
> + dm_i2c_write(dev, TUSB_PORT_POL_CRTL_REG, &pol_swap_val, 1);
> + else
> + printf("TUSB8042A: Failed to fixup USB HUB.\n");
> +}
> +
> +static int setup_fec(void)
> +{
> + struct iomuxc_gpr_base_regs *gpr =
> + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
> +
> + /* Use 125M anatop REF_CLK1 for ENET1, not from external */
> + clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
> +
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION)
> + int ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR);
> +
> + if (ret)
> + printf("%s: EEPROM data init failed\n", __func__);
> +#endif
> + tusb8042a_swap_lines();
> +
> + setup_fec();
> +
> + return 0;
> +}
> +
> +int board_mmc_get_env_dev(int devno)
> +{
> + return devno;
> +}
> +
> +int board_late_init(void)
> +{
> + switch (get_boot_device()) {
> + case SD2_BOOT:
> + env_set_ulong("mmcdev", 1);
> + if (!strcmp(env_get("boot_targets"),
> env_get_default("boot_targets")))
> + env_set("boot_targets", "mmc1 mmc2 ethernet");
> + break;
> + case MMC3_BOOT:
> + env_set_ulong("mmcdev", 2);
> + break;
> + case USB_BOOT:
> + printf("Detect USB boot. Will enter fastboot mode!\n");
> + if (!strcmp(env_get("bootcmd"), env_get_default("bootcmd")))
> + env_set("bootcmd", "fastboot 0; bootflow scan -lb;");
> + break;
> + default:
> + break;
> + }
> +
> + return 0;
> +}
> +
> +int board_phys_sdram_size(phys_size_t *size)
> +{
> + if (!size)
> + return -EINVAL;
> +
> + *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE +
> PHYS_SDRAM_2_SIZE);
> +
> + return 0;
> +}
> diff --git a/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env
> b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env
> new file mode 100644
> index 000000000000..edcd05aedd2e
> --- /dev/null
> +++ b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env
> @@ -0,0 +1,30 @@
> +bootmeths=script
> +boot_targets=mmc2 mmc1 ethernet
> +boot_script_dhcp=boot.scr.uimg
> +bootenv_addr_r=0x49100000
> +console=ttymxc3,115200
> +emmc_dev=2 /* This is needed by built-in uuu flash scripts */
> +fdt_addr_r=0x48000000
> +fdtfile=CONFIG_DEFAULT_FDT_FILE
> +fdtoverlay_addr_r=0x49000000
> +fit_fdtconf=conf-imx8mp-libra-rdk-fpsc.dtb
> +ip_dyn=no
ip_dyn=yes
> +ipaddr=192.168.3.11
remove this line
> +kernel_addr_r=0x5A080000
> +kernel_comp_addr_r=0x60000000
> +kernel_comp_size=0x2000000
> +mmcautodetect=yes
> +mmcdev=CONFIG_SYS_MMC_ENV_DEV
> +mmcpart=1
> +mmcroot=2
> +netmask=255.225.255.0
remove this line
> +nfsroot=/srv/nfs
> +no_bootenv=0
> +no_extensions=0
remove these 2 lines, they add no value
> +pxefile_addr_r=0x58600000
> +ramdisk_addr_r=0x5e000000
> +sd_dev=1 /* This is needed by built-in uuu flash scripts */
> +script_offset_f=0x400000
> +script_size_f=0x2000
> +scriptaddr=0x58500000
> +serverip=192.168.3.10
remove this line
> diff --git a/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c
> b/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c
> new file mode 100644
> index 000000000000..dd5b4ad8347a
> --- /dev/null
> +++ b/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c
Can we reuse the phycore-imx8mp timings?
> @@ -0,0 +1,1846 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright 2019 NXP
> + *
> + * Generated code from MX8M_DDR_tool
> + *
> + * Align with uboot version:
> + * imx_v2019.04_5.4.x and above version
> + * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
> + * please replace #include <asm/arch/ddr.h> with #include
> <asm/arch/imx8m_ddr.h>
> + */
> +
> +
[...]
> diff --git a/board/phytec/imx8mp-libra-fpsc/spl.c b/board/phytec/imx8mp-libra-
> fpsc/spl.c
> new file mode 100644
> index 000000000000..c3e0abf74b42
> --- /dev/null
> +++ b/board/phytec/imx8mp-libra-fpsc/spl.c
> @@ -0,0 +1,131 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (C) 2025 PHYTEC Messtechnik GmbH
> + */
> +
> +#include <config.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/ddr.h>
> +#include <asm/arch/imx8mp_pins.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/global_data.h>
> +#include <asm/mach-imx/boot_mode.h>
> +#include <asm/mach-imx/gpio.h>
> +#include <asm/mach-imx/mxc_i2c.h>
> +#include <asm/mach-imx/iomux-v3.h>
> +#include <hang.h>
> +#include <init.h>
> +#include <log.h>
> +#include <power/pmic.h>
> +#include <power/pca9450.h>
> +#include <spl.h>
> +
> +#include "../common/imx8m_som_detection.h"
This needs the same guard that is present in imx8mp-libra-fpsc.c
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define EEPROM_ADDR 0x51
> +
> +int spl_board_boot_device(enum boot_device boot_dev_spl)
> +{
> + return BOOT_DEVICE_BOOTROM;
> +}
> +
> +void spl_dram_init(void)
> +{
same here
> + int ret;
> +
> + ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR);
> + if (ret)
> + goto out;
> +
> + ret = phytec_imx8m_detect(NULL);
> + if (!ret)
> + phytec_print_som_info(NULL);
> +out:
to here
> + ddr_init(&dram_timing);
> +}
> +
> +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
> +struct i2c_pads_info i2c_pad_info1 = {
> + .scl = {
> + .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
> + .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
> + .gp = IMX_GPIO_NR(5, 14),
> + },
> + .sda = {
> + .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
> + .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
> + .gp = IMX_GPIO_NR(5, 15),
> + },
> +};
> +
> +int power_init_board(void)
> +{
> + struct pmic *p;
> + int ret;
> +
> + ret = power_pca9450_init(0, 0x25);
> + if (ret)
> + printf("power init failed");
> + p = pmic_get("PCA9450");
> + pmic_probe(p);
> +
> + /* BUCKxOUT_DVS0/1 control BUCK123 output */
> + pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
> +
> + /* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */
> + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
> + pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
> +
> + /* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */
> + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
> + pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
> +
> + /* Set WDOG_B_CFG to cold reset */
> + pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
> +
> + return 0;
> +}
> +
> +void spl_board_init(void)
> +{
> + arch_misc_init();
> +
> + /* Set GIC clock to 500Mhz for OD VDD_SOC. */
> + clock_enable(CCGR_GIC, 0);
> + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
> CLK_ROOT_SOURCE_SEL(5));
> + clock_enable(CCGR_GIC, 1);
> +}
> +
> +int board_fit_config_name_match(const char *name)
> +{
> + return 0;
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> + int ret;
> +
> + arch_cpu_init();
> +
> + init_uart_clk(3);
This is not needed anymore. Remove this and set appropriate configs to use the
clock framework.
> +
> + ret = spl_early_init();
> + if (ret) {
> + debug("spl_early_init() failed: %d\n", ret);
> + hang();
> + }
> +
> + preloader_console_init();
> +
> + enable_tzc380();
> +
> + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
> +
> + power_init_board();
> +
> + /* DDR initialization */
> + spl_dram_init();
> +}
> diff --git a/configs/imx8mp-libra-fpsc_defconfig b/configs/imx8mp-libra-
> fpsc_defconfig
> new file mode 100644
> index 000000000000..7b3c3e6f5d62
> --- /dev/null
> +++ b/configs/imx8mp-libra-fpsc_defconfig
> @@ -0,0 +1,170 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_IMX8M=y
> +CONFIG_TEXT_BASE=0x40200000
> +CONFIG_SYS_MALLOC_LEN=0x2000000
> +CONFIG_SPL_GPIO=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SF_DEFAULT_SPEED=80000000
> +CONFIG_ENV_SIZE=0x10000
> +CONFIG_ENV_OFFSET=0x3C0000
> +CONFIG_ENV_SECT_SIZE=0x10000
> +CONFIG_SYS_I2C_MXC_I2C1=y
> +CONFIG_DM_GPIO=y
> +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-libra-rdk-fpsc"
> +CONFIG_TARGET_IMX8MP_LIBRA_FPSC=y
> +CONFIG_OF_LIBFDT_OVERLAY=y
> +CONFIG_SYS_MONITOR_LEN=524288
> +CONFIG_SPL_MMC=y
> +CONFIG_SPL_SERIAL=y
> +CONFIG_SPL_DRIVERS_MISC=y
> +CONFIG_SPL_STACK=0x960000
> +CONFIG_SPL_TEXT_BASE=0x920000
> +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
> +CONFIG_SPL_BSS_START_ADDR=0x98fc00
> +CONFIG_SPL_BSS_MAX_SIZE=0x400
> +CONFIG_SYS_LOAD_ADDR=0x40480000
> +CONFIG_SPL=y
> +CONFIG_ENV_OFFSET_REDUND=0x3e0000
> +CONFIG_IMX_BOOTAUX=y
> +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
> +# CONFIG_ANDROID_BOOT_IMAGE is not set
> +CONFIG_FIT=y
> +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_BOOTSTD_FULL=y
> +CONFIG_OF_SYSTEM_SETUP=y
> +CONFIG_FDT_FIXUP_PARTITIONS=y
> +CONFIG_DEFAULT_FDT_FILE="oftree"
Change this to "imx8mp-libra-rdk-fpsc.dtb"
or omit, please.
> +CONFIG_SYS_CBSIZE=2048
> +CONFIG_SYS_PBSIZE=2074
> +CONFIG_BOARD_LATE_INIT=y
> +CONFIG_SPL_MAX_SIZE=0x26000
> +CONFIG_SPL_BOARD_INIT=y
> +CONFIG_SPL_BOOTROM_SUPPORT=y
> +CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
> +CONFIG_SPL_HAVE_INIT_STACK=y
> +CONFIG_SPL_SYS_MALLOC=y
> +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
> +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
> +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
> +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
> +CONFIG_SPL_I2C=y
> +CONFIG_SPL_NOR_SUPPORT=y
> +CONFIG_SPL_POWER=y
> +CONFIG_SPL_WATCHDOG=y
> +CONFIG_SYS_PROMPT="u-boot=> "
> +CONFIG_CMD_ERASEENV=y
> +CONFIG_CMD_EEPROM=y
> +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
> +CONFIG_SYS_EEPROM_SIZE=4096
> +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
> +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
> +CONFIG_CMD_CLK=y
> +CONFIG_CMD_FUSE=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_MTD=y
> +CONFIG_CMD_SF_TEST=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_USB_SDP=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_MTDPARTS=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_OF_UPSTREAM=y
> +CONFIG_ENV_OVERWRITE=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_ENV_REDUNDANT=y
> +CONFIG_ENV_RELOC_GD_ENV_ADDR=y
> +CONFIG_ENV_MMC_DEVICE_INDEX=2
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_SPL_DM=y
> +CONFIG_CLK_COMPOSITE_CCF=y
enable the spl version of this to utilize clock framework in spl.
See above in .spl comment.
> +CONFIG_CLK_IMX8MP=y
> +CONFIG_FSL_CAAM=y
> +CONFIG_USB_FUNCTION_FASTBOOT=y
> +CONFIG_FASTBOOT_BUF_ADDR=0x42800000
> +CONFIG_FASTBOOT_BUF_SIZE=0x13000000
> +CONFIG_FASTBOOT_FLASH=y
> +CONFIG_FASTBOOT_UUU_SUPPORT=y
> +CONFIG_FASTBOOT_FLASH_MMC_DEV=2
> +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
> +CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc2boot0"
> +CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc2boot1"
> +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
> +CONFIG_FASTBOOT_MMC_USER_NAME="mmc2"
> +CONFIG_MXC_GPIO=y
> +CONFIG_DM_I2C=y
> +# CONFIG_SPL_DM_I2C is not set
> +CONFIG_SPL_SYS_I2C_LEGACY=y
> +CONFIG_I2C_EEPROM=y
> +CONFIG_SYS_I2C_EEPROM_ADDR=0x51
> +CONFIG_SUPPORT_EMMC_BOOT=y
> +CONFIG_MMC_IO_VOLTAGE=y
> +CONFIG_MMC_UHS_SUPPORT=y
> +CONFIG_MMC_HS400_ES_SUPPORT=y
> +CONFIG_MMC_HS400_SUPPORT=y
> +CONFIG_FSL_USDHC=y
> +CONFIG_MTD=y
> +CONFIG_DM_MTD=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SPI_FLASH_BAR=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_SPI_FLASH_SST=y
> +CONFIG_SPI_FLASH_WINBOND=y
> +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
> +CONFIG_SPI_FLASH_MTD=y
> +CONFIG_PHY_TI_DP83867=y
> +CONFIG_DM_ETH_PHY=y
> +CONFIG_PHY_GIGE=y
> +CONFIG_DWC_ETH_QOS=y
> +CONFIG_DWC_ETH_QOS_IMX=y
> +CONFIG_FEC_MXC=y
> +CONFIG_RGMII=y
> +CONFIG_MII=y
> +CONFIG_PHY_IMX8MQ_USB=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_PINCTRL_IMX8M=y
> +CONFIG_SPL_POWER_LEGACY=y
> +CONFIG_POWER_DOMAIN=y
> +CONFIG_IMX8M_POWER_DOMAIN=y
> +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
> +CONFIG_POWER_PCA9450=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_SPL_POWER_I2C=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_MXC_UART=y
> +CONFIG_SPI=y
> +CONFIG_DM_SPI=y
> +CONFIG_NXP_FSPI=y
> +CONFIG_SYSRESET=y
> +CONFIG_SPL_SYSRESET=y
> +CONFIG_SYSRESET_PSCI=y
> +CONFIG_SYSRESET_WATCHDOG=y
> +CONFIG_DM_THERMAL=y
> +CONFIG_USB=y
> +CONFIG_DM_USB_GADGET=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_XHCI_DWC3=y
> +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_DWC3_GENERIC=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
> +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
> +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
> +CONFIG_IMX_WATCHDOG=y
> diff --git a/include/configs/imx8mp-libra-fpsc.h b/include/configs/imx8mp-
> libra-fpsc.h
> new file mode 100644
> index 000000000000..fa06eaf058a8
> --- /dev/null
> +++ b/include/configs/imx8mp-libra-fpsc.h
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * Copyright (C) 2025 PHYTEC Messtechnik GmbH
> + */
> +
> +#ifndef __IMX8MP_LIBRA_H
> +#define __IMX8MP_LIBRA_H
#define __IMX8MP_LIBRA_FPSC_H
> +
> +#include <linux/sizes.h>
> +#include <asm/arch/imx-regs.h>
> +
> +#define CFG_SYS_UBOOT_BASE \
> + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR *
> 512)
> +
> +/* Link Definitions */
> +
> +#define CFG_SYS_INIT_RAM_ADDR 0x40000000
> +#define CFG_SYS_INIT_RAM_SIZE SZ_512K
> +
> +#define CFG_SYS_SDRAM_BASE 0x40000000
> +
> +#define PHYS_SDRAM 0x40000000
> +#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) /* 3GB */
> +#define PHYS_SDRAM_2 0x100000000
> +#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) /* 5GB */
> +
> +#endif /* __IMX8MP_LIBRA_H */
fix here as well.
Yannic
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