[PATCH 4/9] ddr: imx9: Disable dynamic refresh rate when do mr operation

[Fabio Estevam]

On Sun, Jul 27, 2025 at 11:14 PM Peng Fan (OSS) <peng.fan at oss.nxp.com> wrote:
>
> From: "haidong.zheng" <haidong.zheng at nxp.com>


Haidong Zheng


>
> On i.MX93/91, dynamic refresh rate should be disabled before doing any
> MR read or write. Otherwise conflict may happen with read MR12/MR14 in
> ddr_init.
> We randomly meet DDR unstable with low drive mode frequencies and 1600MTS
> DDR setting on iMX91. With this fix, the issue is gone.
>
> Signed-off-by: haidong.zheng <haidong.zheng at nxp.com>

Haidong Zheng

> Tested-by: Ye Li <ye.li at nxp.com>
> Reviewed-by: Jacky Bai <ping.bai at nxp.com>
> Signed-off-by: Peng Fan <peng.fan at nxp.com>
> ---
>  drivers/ddr/imx/imx9/ddr_init.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
> index 5a134dda78a331c21d4a75b2369c5b9314028bbc..42ba493ebca4d6efc5ee047dd3f049cebb24b69d 100644
> --- a/drivers/ddr/imx/imx9/ddr_init.c
> +++ b/drivers/ddr/imx/imx9/ddr_init.c
> @@ -266,6 +266,11 @@ void update_umctl2_rank_space_setting(struct dram_timing_info *dram_timing, unsi
>  u32 ddrc_mrr(u32 chip_select, u32 mode_reg_num, u32 *mode_reg_val)
>  {
>         u32 temp;
> +       u8 dyn_ref_rate_en = 0;
> +
> +       dyn_ref_rate_en = !!(readl(REG_DDR_SDRAM_CFG_3) & BIT(7));

Can you add a define for this BIT(7)?