[PATCH 00/10] rockchip: Fix misc USB PHY related issues

[Quentin Schulz]

Hi Jonas,

On 7/22/25 12:07 AM, Jonas Karlman wrote:
> This series tries to fix a few USB PHY related issues found while
> working on RK3528/RK3576 USB OTG support.
> 
> The first issue is related to Generic PHY reference counting that is not
> working correctly for the usbdp or naneng-combphy drivers. Both drivers
> xlate ops never initialized phy->id so it could initialize with an old
> value from stack when the dwc3-generic driver was probed, causing two
> struct phy to be initialized and ending up not sharing same phy->id,
> resulting in reference counting for init/exit and power on/off not
> working properly.
> 
> The second issue is related to the two inno-usb2 and typec drivers
> improperly used UCLASS_PHY for their glue/wrapper driver. This could
> cause a crash in very specific scenarios, e.g. missing to enable the
> otg/host-port node and only leaving the usb2phy node enabled.
> 
> The last issue is related to supporting using only USB2 PHY for USB OTG
> purpose without having the USB3 PHY initialized, in such scenario the U3
> port needs to be disable, more precisely the usb3otg clock source must
> change to use UTMI clk instead of the default PIPE clk.
> 
> Prior to this series it was the usb3-phy related driver that would
> disable the U3 port in special circumstances, e.g. for DP only mode or
> when limiting to use high-speed as maximum-speed.
> 
> With this series the U3 port instead is disabled early, the USBDP PHY
> driver in both U-Boot and Linux will already enable the U3 port when
> needed so no changes in behavior is really expected for boards.
> 
> Finally, this series also moves usb otg related device tree nodes for
> the Generic RK3588 board from the board u-boot.dtsi to the main board
> dts.
> 

I recently tested 2025.07 on RK3588 Tiger and realized that one of the 
three USB ports isn't actually working.

I get:

"""
=> usb reset
resetting USB...
USB EHCI 1.00
USB OHCI 1.0
USB EHCI 1.00
USB OHCI 1.0
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
rockchip_udphy phy at fed90000: cmn ana lcpll lock timeout
rockchip_udphy phy at fed90000: failed to init usbdp combophy
rockchip_udphy phy at fed90000: PHY: Failed to init phy at fed90000: -110.
Can't init PHY1
Bus usb at fc400000: probe failed, error -110
Bus usb at fc800000: 2 USB Device(s) found
Bus usb at fc840000: 1 USB Device(s) found
Bus usb at fc880000: 2 USB Device(s) found
Bus usb at fc8c0000: 1 USB Device(s) found
Bus usb at fcd00000: 1 USB Device(s) found
        scanning usb for storage devices... 2 Storage Device(s) found
=>
"""

The port that doesn't work is the one that has USB3 over the usbdp_phy1 
and the USB2 part through u2phy1_otg, both going through usb_host1_xhci 
DWC3 USB controller.

Applying the whole series fixes that, so I guess I can say:

Tested-by: Quentin Schulz <quentin.schulz at cherry.de> # RK3588 Tiger Haikou

Thanks!
Quentin